Silicon-on-insulator Structure Research Articles

Transfer of physically-based models from process to device simulations: Application to advanced SOI MOSFETs

Dopant implantation, followed by spike annealing is one of the main focus areas in the simulation of silicon processing due to its ability to form highly-activated ultra-shallow junctions. Coupled with the growing interest in the use of silicon-on-insulator (SOI) wafers, modelling and simulation of the influence of SOI structure on damage evolution and ultra-shallow junction formation on one hand, and on electrical MOSFET device characteristics on the other hand, are required. In this work, physically-based models of dopant implantation and diffusion, including amorphization, defect interactions and evolution, as well as dopant–defect interactions in both bulk silicon and SOI are integrated within a unique simulation tool to model the different physical mechanisms involved in the process of ultra-shallow junction formation. The application to 65 nm SOI MOSFET devices demonstrated the strong impact of the process simulation models on the simulated electrical device characteristics, in particular for both defect evolution and defect dopant interaction with the additional silicon/buried oxide (Si/BOX) interface. Simulation results of the threshold voltage ( V th) and the variation of the on- and off-state currents of the explored structures are in good agreement with experimental data and can provide important insight for optimizing the process in both bulk silicon and SOI technologies.

Structural Characterization of Arsenic Implanted SOI

Solid phase epitaxy re-growth of arsenic implanted in silicon on insulator (SOI) was studied by Rutherford Backscattering Spectrometry and Transmission Electron Microscopy. Two SOI structures with different Si overlayer and buried oxide thicknesses were used. The As+ implantations were performed with a single energy of 20 keV to a dose of 5x1014 cm-2 in both substrates. A plateau-like profile was achieved in an additional set of SOI samples by triple energy implantation. Rapid thermal annealing and conventional furnace annealing were applied for re-crystallization and dopant activation. The results are discussed considering the amorphization depth reached by dopant implantation and the crystal recovery process via thermal treatment.

Nanoplate field-effect capacitive (bio-)chemical sensor array based on SOI structure

An array of individually addressable nanoplate field-effect capacitive (bio-)chemical sensors based on an SOI (silicon-on-insulator) structure has been developed for multi-parameter detection. An isolation of the individual capacitors was achieved by forming a trench in the top Si layer with various thicknesses of 30-350 nm. The feasibility of the proposed approach has been demonstrated by realising sensors for the detection of pH as well as for the label-free electrical monitoring of adsorption and binding of charged macromolecules.

Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bg</sub> , resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bg</sub> only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 V/mum of the conventional SOI to 457 V/mum at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bg</sub> = 0 V, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO.

Applications of plasma-based technology to microelectronics and biomedical engineering

Plasma-based ion implantation and deposition techniques are widely used in many applications. In addition to the ability to modify the materials surface, novel structures can be fabricated. Another advantage is that the surface characteristics such as mechanical properties and biocompatibility can be selectively enhanced with the favorable bulk attributes of the materials unchanged. In this invited paper, our recent research activities on microelectronics and biomedical engineering are reviewed. Silicon-on-insulator (SOI) is expected to replace conventional bulk silicon substrates in many high speed, low power microelectronic devices because it possesses advantages such as reduction of parasitic capacitance, excellent sub-threshold slope, elimination of latch up, and resistance to radiation. However, wider applications of SOI in microelectronics are hampered by the self-heating effects caused by the poor thermal conductivity of the buried silicon dioxide layer. We have produced alternative buried insulators such as diamond-like carbon that possesses better thermal conductivity compared to conventional silicon dioxide using plasma immersion ion implantation and deposition (PIII&D) and successfully fabricated SOI structures with improved thermal stability. The use of low-energy plasma hydrogenation to substitute for the costly beam-line hydrogen ion implantation in the ion-cutting layer transfer technology is also discussed. In biomedical engineering, plasma spraying is a versatile technique to produce relatively thick ceramic coatings on orthopedic implant surfaces. We have discovered that plasma-sprayed nano-structured TiO 2 coatings favor the growth of apatite. The surface bioactivity is enhanced by hydrogen plasma implantation and the mechanism is discussed. The antibacterial properties of polymers can also be improved by implanting elements such as Ag and Cu and recent work in our laboratory is described.

Effect of swift heavy ion (SHI) irradiation on nitrogen ion implanted silicon

The synthesis of buried silicon nitride insulating layers was carried out by SIMNI (separation by implanted nitrogen) process using implantation of 140 keV nitrogen ( 14N +) ions at fluence of 5.0 × 10 17 cm − 2 at room temperature with current density of 45–46 µA-cm − 2 into <111> single crystal silicon substrates. To study the swift heavy ion (SHI) induced recrystallization of SOI (Silicon-on-insulator) structures, the implanted samples were irradiated with 60 MeV Ni +5 ions with fluence of 1.0 × 10 14 cm − 2 at high temperature (270 °C). The Micro-Raman spectra show distinct peaks assigned to transverse acoustical (TA) and transverse optical (TO) vibration bands of amorphous silicon. The HRXRD studies show that the full width at half maximum (FWHM) of irradiated samples increases with respect to virgin silicon and the samples remain amorphous even after SHI irradiation.

SiC Freestanding Micromechanical Structures on Silicon-On-Insulator Substrates

The fabrication of freestanding SiC microstructures on Silicon-On-Insulator (SOI) and semi-insulating Silicon substrates is reported. SiC layers were grown on SOI and semi-insulating Si by chemical vapour deposition (CVD) and to avoid the instability currently obtained in SOI structures, the growth process parameters have been optimized. Isotropic wet chemical etching of the Si sacrificial layer released the electrostatic SiC microstructures patterned by dry etching. Moreover a new concept for reducing the gap between resonators and electrodes by the uses of bistable mobile electrodes is introduced.

Possibility of SOI Fabrication Using Plasma Source Ion Implantation with High-Power Pulsed RF Plasma

Silicon-on-insulator (SOI) structure fabricated by plasma source ion implantation (PSII) with high-power pulsed RF plasma has been studied. Oxygen ions were implanted into p-type silicon wafer and high temperature annealing was subsequently used to form SOI structure. The top silicon and the buried oxide (BOX) layer were formed with 500 Å and 400 Å, respectively, in the sample implanted with the dose of 2.5 × 1017 #/cm2 at the ion energy of -75 kV and annealed at 1350 °C for 30 min in Ar+O2 (0.5 %) ambient. This study showed the possibility of SOI fabrication using the PSII with pulsed ICP source.

Endotaxial growth of InSb nanocrystals at the bonding interface of the In+ and Sb+ ion implanted SOI structure

Growth of InSb nanocrystals at the Si/SiO2 bonding interface of silicon-on-insulator (SOI) structures has been studied as a function of the annealing temperature. SOI structures with the ion implanted regions above and below the bonding interface were produced as a result of the hydrogen transfer of the Sb+ ion implanted silicon layer from first silicon substrate to the In+ ion implanted SiO2 layer thermally-grown on the second silicon substrate. Rutherford backscattering spectrometry and high-resolution transmission electron microscopy (XTEM) were used to study the properties of the prepared structures. Up-hill diffusion of In and Sb atoms from the implantation regions toward the bonding interface as well as subsequent interface-mediated growth of InSb nanocrystals were observed as the annealing temperature achieved 1100°C. The strain minimizing orientations of the Si and InSb lattice heteropairs were obtained from XTEM analysis of the grown nanocrystals.

Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

This work presents the optimal design of a silicon-on-insulator (SOI) diode structure to eliminate the back gate bias effect and to improve breakdown voltage. The SOI structure is characterized by inserting a silicon low doping buried layer (LDBL) between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter that affects the strong inversion condition of the back MOS capacitor of the new SOI diode. The optimal LDBL thickness in the SOI diode is 2.65μm. The LDBL shielding layer improved the breakdown voltage.

Study of SHI induced recrystallization effects in SOI structures synthesized by nitrogen and oxygen ion implantation in silicon

Silicon oxynitride (Si x O y N z ) buried insulating layers were synthesized by implantation of nitrogen ( 14N +) and oxygen ( 16O +) ions sequentially in the ratio 1:1 at 150 keV to ion-fluences ranging from 1 × 10 17 to 5 × 10 17 cm −2 to prepare silicon on insulator (SOI) structures. The as implanted samples were held at 270 °C and irradiated to total fluence of 1 × 10 14 cm −2 by 60 MeV Ni +5 to study the structural changes/recrystallization of SOI structures induced by swift heavy ion (SHI) irradiation. Fourier transform infrared (FTIR) measurements on the as implanted samples (≤1 × 10 18 cm −2) show a single absorption band in the wavenumber range 1300–750 cm −1 attributed to the formation of silicon oxynitride (Si–O–N) bonds in the implanted silicon. It is observed that a nitrogen rich silicon oxynitride structure is formed after SHI irradiation. The study of X-ray rocking curves on the samples show the formation of small silicon crystallites due to swift heavy ion irradiation.

Optimum Design for Eliminating Back Gate Bias Effect of Silicon-oninsulator Lateral Double Diffused Metal-oxide-semiconductor Field Effect Transistor with Low Doping Buried Layer

An optimum design with silicon-on-insulator (SOI) device structure was proposed to eliminate back gate bias effect of the lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) and to improve breakdown voltage. The SOI structure was characterized by low doping buried layer (LDBL) inserted between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter to affect the strong inversion condition in the back MOS capacitor of the new SOI diode. The optimum design of LDBL thickness for the SOI diode was 2.65 μm. Fur- thermore, the breakdown capability has been improved 11%. However, no analysis of device physic has been so far given for the substrate bias effect on SOI device breakdown voltage. In this paper, the analysis of the substrate bias effect for the lateral and vertical surface potential and electric field distribution in the off-state is firstly proposed, and a novel SOI device structure with a low doping buried layer (LDBL) is employed to eliminate the substrate bias effect. The 2-D simulations for the substrate effect are performed using the tool ISE-TCAD (9). BACK GATE BIAS EFFECT IN THE SOI DEVICE

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured.

An Analytical Model for Silicon-on-Insulator Reduced Surface Field Devices with Semi-Insulating Polycrystalline Silicon Shielding Layer

An analytical model is presented to determine the potential and electric field distribution along the semiconductor surface of new silicon-on-insulator (SOI) reduced surface field (RESURF) device. The SOI structure is characterized by a semi-insulating polycrystalline silicon (SIPOS) layer inserted between a silicon layer and a buried oxide. An improvement in the breakdown voltage due to the presence of the SIPOS shielding layer is demonstrated. Numerical simulations using medici are shown to support the analytical model.

Characterization of Patterned Oxide Buried in Bonded Silicon-on-Insulator Wafers by Near-Infrared Scattering Topography and Microscopy

A patterned oxide buried in bonded silicon-on-insulator (SOI) wafers before thinning has been characterized using a near-infrared scattering topography system. This system has been combined with transmission and reflection microscopy. The edge of the patterned oxide buried in the SOI wafer has been observed. Micron-scaled oxide disks formed by the focused ion beam technique in stacked SOI structures have been observed by near-infrared scattering topography. A particle has been identified to be located inside a silicon/air/silicon structure by both near-infrared and visible laser scattering topographies. The size of the particle inside the silicon/air/silicon structure has been estimated to be 0.2 µm from the intensity of scattered near-infrared light. This method has an advantage over semiconductor failure analysis in future scaled-down technologies.

Defect evolution after germanium preamorphization in silicon on insulator structures

Experimental data obtained in bulk and silicon on insulator (SOI) structures by transmission electron microscopy (TEM) are reported showing that the density of extended defects in SOI structures is reduced in comparison with bulk silicon. Additional data obtained on strained SOI structures show that a less pronounced reduction is observed in these structures. It will also be shown that simulations based on an already existing model and taking into account the effect of the Si/BOX interface acting as a sink for interstitials are not able to explain the experimentally observed defect density reduction in unstrained SOI.

Application of electron holography to analysis of submicron structures

Importance of effects of charging and sample thickness variation across depletion region is discussed using one-dimensional p-n junction in bulk Si and silicon-on-insulator (SOI) structures prepared by mechanical polishing. It is shown that good correlation between results of electron holography and secondary ion mass spectroscopy can be achieved without consideration of “dead layers.” Analysis of laser annealed n-type field-effect transistor (n-FET) devices in SOI structures showed that laser annealing does not cause lateral dopant diffusion of arsenic to resolution of electron holography. It is demonstrated that junction overlap can be achieved with “laser-only” integration scheme. Examples are given on how electron holography can provide insight into integration scheme for development of a p-FET device with embedded SiGe source/drain regions and evaluation of effect of proximity of shallow trench isolation on dopant depletion.

A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations

An actively body-bias controlled (ABC) silicon-on-insulator (SOI) static random access memory (SRAM) connecting the bodies of the access and the driver transistors with the word line is proposed to realize high-speed and low-voltage operation. We developed the direct body contact to apply forward biases to the bodies without increases in the area penalty and the parasitic gate capacitance. An increase of the standby current does not occur because the body biases are not applied when the word-line voltage is low level. It is demonstrated that a significant speed improvement and a reduction of performance variations for the SRAM are achieved by applying the body bias. Neutron-accelerated soft-error tests reveal that the ABC structure suppresses soft-error events due to the body-tied SOI structure. In summary, the ABC SOI technology is one of the countermeasures for emerging generations.

Fabrication of Thermoelectric Sensor Using Silicon-on-Insulator Structure

In this paper, we present a thermally measurable contact and noncontact-type thermoelectric sensor using a silicon-on-insulator (SOI) structure, because single-crystal silicon has a higher Seebeck coefficient than any other thermoelectric material. The sensor was designed to have 17 pairs of n- and p-type single-crystal silicon strips and a selective absorption area (SAA) that consists of aluminum and silicon dioxide. The thermoelectric sensor based on the SOI structure was fabricated and measured using a complementary metal–oxide–semiconductor (CMOS) process. The measured sensitivity of the sensor was 0.19 mV/°C, when human skin directly touched the sensor surface. In the noncontact measurement of the sensor while varying the distance between the lamp (EFD10EL/8, NEC) and the sensor, the maximum electromotive force (EMF) of the sensor was -1.55 mV at a 2 mm (6.09 mW) distance.

SiGe Heterostructures-on-Insulator Produced by Ge&lt;sup&gt;+&lt;/sup&gt;-Ion Implantation and Subsequent Hydrogen Transfer

The properties of germanium implanted into the SiO2 layers in the vicinity of the bonding interface of silicon-on-insulator (SOI) structures are studied. It is shown that no germanium nanocrystals are formed in the buried SiO2 layer of the SOI structure as a result of annealing at the temperature of 1100° C. The implanted Ge atoms segregate at the Si/SiO2 bonding interface. In this case, Ge atoms are found at sites that are coherent with the lattice of the top silicon layer. It is found that the slope of the drain–gate characteristics of the back metal-oxide-semiconductor (MOS) transistors, prepared in the Ge+ ion implanted structures, increases. This effect is attributed to the grown hole mobility due to the contribution of an intermediate germanium layer formed at the Si/SiO2 interface.