Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

Abstract

This work presents the optimal design of a silicon-on-insulator (SOI) diode structure to eliminate the back gate bias effect and to improve breakdown voltage. The SOI structure is characterized by inserting a silicon low doping buried layer (LDBL) between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter that affects the strong inversion condition of the back MOS capacitor of the new SOI diode. The optimal LDBL thickness in the SOI diode is 2.65μm. The LDBL shielding layer improved the breakdown voltage.