Silicon-on-insulator Metal-oxide-semiconductor Field-effect Transistors Research Articles

A novel circular double-gate SOI MOSFET with raised source/drain

In this paper, we report the performance of a novel circular double-gate (CDGT) silicon-on-insulator metal oxide semiconductor field effect transistor (MOSFET). We explore a variety of device configurations that are possible by making changes in the pad height in terms of a raised top, bottom, or top and bottom (both). The results demonstrate that the best device configuration is a raised both CDGT with an internal pad as a drain. For the above configuration, the impact of a junctionless mode is further analyzed and the optimum performance is obtained with a doping level of 1 × 1018 cm−3. The device exhibits good electrical characteristics, with an ON/OFF current ratio of 3.73 × 105, a near-ideal subthreshold slope of 66.9 mV dec−1, and a small drain-induced barrier lowering of ∼35 mV V−1. Among various circular MOSFETs, the CDGT device exhibits an optimum delay performance of 2 ps based on a two-stage inverter analysis.

Applications of Direct-Current Current–Voltage Method to Total Ionizing Dose Radiation Characterization in SOI NMOSFETs with Different Process Conditions

As a promising candidate in space radiation hardened applications, silicon-on-insulator (SOI) devices face the severe problem of total ionizing dose (TID) radiation because of the thick buried oxide (BOX) layer. The direct-current current–voltage (DCIV) method was applied for studying TID radiation of SOI metal–oxide–semiconductor field–effect transistors (MOSFETs) with different manufacture processes. It is found that the peak of high-voltage well (PX) devices shows a larger left-shift and a slower multitude increase along with radiation dose, compared with that of low-voltage well (PV) devices. It is illustrated that the high P-type impurity concentration near back interface makes it more difficult to break up silicon hydrogen bonds, which gives the PX devices superiority in resisting the build-up of interface traps. The study results indicate that increasing doping concentration of the body region near the back-gate interface might be an alternative radiation hardening technique of SOI MOSFET devices to avoid the parasitic back transistors’ leakage.

Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL).

Implementing expanded source doping to improve performance of a nano-scale fully depleted silicon on insulator transistor

IIn this paper, we proposed a short channel Silicon on Insulator Metal-oxide Semiconductor-Field-Effect-Transistor (SOI-MOSFET), in which a thin layer of n+-type doping has been expanded from top of its entire source region into the channel and also a proportionally heavily p-type retrograde doping has been implanted in its channel, close to the source region. Due to source doping expansion in the channel, we call this structure as Source Expanded Doping Silicon on Insulator (SED-SOI) structure. This expanded n+ doping increases the carrier concentration in the source, which can be injected into the channel. Moreover, it increases the amount of carriers, which can be controlled more effectively by the gate electrode. These two advantages enhance both ON state current and transconductance in the device more than 1.9 mA and 5 mS, respectively. Engineered p-type retrograde doping profile causes impurity scattering and this reduces electron mobility in the depth of the device channel, which in turn OFF current decreases down to 0.2 nA. An immense comparison among our proposed device and a conventional structure (C-SOI) shows that it has better performance in terms of Ion/Ioff ratio (>9.5×105), subthreshold swing (75 mV/dec), leakage current, breakdown voltage, hot carrier injection and DIBL. Our analysis demonstrate that SED-SOI transistor can be an excellent candidate for both low power and high performance applications.

A Compact Analytical Drain Current Model of Fully Depleted SOI MOSFETs with Lightly Doped N- underneath the N+ Source Region

In this work, we report a 2-D analytical model for threshold voltage and drain current of fully depleted silicon-on-insulator (SoI) metal oxide semiconductor field-effect transistor (MOSFET) with lightly doped N- underneath the N+ source region. This model considers the effect of oxide thickness, source doping variations and silicon film thickness. The accuracy of the proposed model is verified using 2-D numerical simulations in terms of surface potential, threshold voltage and drain current. In comparison with the conventional FD SOI devices, the proposed model predicts that modified source based FD SOI structure gives better OFF-state current, improved ON-state to OFF-state current (ION/IOFF ~ 109) ratio.

Monolithic 3D Integration of InGaAs Photodetectors on Si MOSFETs Using Sequential Fabrication Process

We demonstrated the monolithic 3D (M3D) integration of InGaAs photodetectors (PDs) on silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI-MOSFETs) by the sequential process of InGaAs PDs on pre-fabricated SOI-MOSFETs. InGaAs PDs and SOI MOSFETs showed their original performances after integration and sequential process thanks to the low-temperature process. In addition, the integrated devices successfully performed the fundamental readout circuit operation such as direct injection and source follower per detector (SFD) by connecting transistors (Trs) and PDs. By illuminating 1550 nm laser on InGaAs PDs, the different behaviors of output voltages were clearly obtained according to the Tr’s on/off state. From these results, we believe that this monolithic 3D integration method could be a feasible approach toward high-resolution multicolor imaging systems.

Grooved-gate silicon-on-nothing (SON) MOSFET: evidence for suppressing SCEs

This paper presents a simulation-based systematic characterization of a dual-metal-stack grooved-step-gate (DMS-GSG) silicon-on-nothing (SON) metal–oxide–semiconductor field-effect transistor (MOSFET) with stack buried oxide (SBO) for restraining short-channel effects (SCEs). Comparison was done between silicon-on-insulator (SOI) and SON SBO grooved-gate (GG) MOSFETs to realize the feasibility of the presented structure. Analysis of thermal stability over a wide range of temperatures was carried out for better characterization of the proposed structure. Further, the impact of structural parameters such as the negative junction depth and the influence of the work-function difference on the threshold voltage, drain current and drain-induced barrier lowering were analyzed. The investigation revealed that the DMS-GSG SON MOSFET is more prominent than other GG SOI MOSFETs in terms of switching behavior, SCEs, hot-carrier effect, intrinsic gain and early voltage. Further, the presence of air in the SBO of the DMS-GSG SON MOSFET suppresses the self-heating effect. Thus, this in-depth investigation is relatively beneficial to find out the performance improvement of SON structures over SOI ones for nanoscale short-channel devices.

A nanoscale silicon on insulator transistor with superior performance using dual material gate and retrograde/halo doping in source/drain sides

This paper introduces two novel structures for silicon on insulator (SOI) metal-oxide-semiconductor field effect transistor (SOI-MOSFET) with nanoscale dimension and superior electrical performance. One structure only incorporates retrograde halo dopants (RHD) in the source side and uniform halo dopants in the drain side. The other device comprises dual material (DM) in the gate contact along with RHD in the source side and uniform halo dopants in the drain side (DM-RHD). Incorporation of retrograde dopants in the source side and uniform doping in the drain side of RHD and DM-RHD lead to improvements in the leakage current, sub-threshold slope and short channel effects. Hot carrier injection to the gate, channel length modulation and drain-induced barrier lowering are significantly improved with respect to the conventional SOI-MOSFET. The auxiliary gate, along with the main gate in the DM-RHD structure, improves off-current control in the channel compared with RHD and C–SOI counterparts. Because the proposed devices show these positive features, they can be utilized to satisfy International Technology Roadmap for Semiconductors requirements for next generation devices.

Effect of Microwave Annealing on the Interface Properties Between the Top Silicon and Buried Oxide Layers in Silicon-on-Insulator MOSFETs

In this paper, a post-annealing process that uses microwaves to remove the back-interface thermal damage at the interface between the top silicon layer and the buried oxide layer of a silicon-on-insulator (SOI) device caused during rapid thermal annealing (RTA) was studied. RTA, which is widely used in highly integrated short-channel silicon device manufacturing processes, deteriorates the electrical characteristics of SOI pseudo metal-oxide-semiconductor field-effect transistors (MOSFET) by affecting the interfacial properties between the top silicon and buried oxide layers. In order to replenish these interfacial properties, microwave annealing (MWA) was performed on the device under various conditions. Because MWA utilizes the direct energy transfer (DET) method, the RTA-induced thermal damage on the back interface was effectively removed despite a short processing time. The improvement was comparable to that of conventional thermal annealing at a higher temperature for a long period of time. Therefore, MWA is expected to be a very effective post-RTA heat-treatment technology for fabricating ultrathin-body SOI MOSFETs because of its low thermal budget.

TCAD Simulation and Analysis of Selective Buried Oxide MOSFET Dynamic Power

Low power consumption has become one of the major requirements for most microelectronic devices and systems. Increasing power dissipation may lead to decreasing system efficiency and lifetime. The BULK metal oxide semiconductor field-effect transistor (MOSFET) has relatively high power dissipation and low frequency response due to its internal capacitances. Although the silicon-on-insulator (SOI) MOSFET was introduced to resolve these limitations, other challenges were introduced including the kink effect in the current-voltage characteristics. The selective buried oxide (SELBOX) MOSFET was then suggested to resolve the problem of the kink effect. The authors have previously investigated and reported the characteristics of the SELBOX structure in terms of kink effect, frequency, thermal and static power characteristics. In this paper, we continue our investigation by presenting the dynamic power characteristics of the SELBOX structure and compare that with the BULK and SOI structures. The simulated fabrication of the three devices was conducted using Silvaco TCAD tools in 90 nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that the average dynamic power dissipation of the CMOS BULK, SOI and SELBOX are compatible at high frequencies with approximately 54.5 µW. At low frequencies, the SOI and SELBOX showed comparable dynamic power dissipation but with lower values than the BULK structure. The difference in power dissipation between the SELBOX and BULK is in the order of nano watts. This power difference becomes significant at the chip level. For instance, at 1 MHz, SOI and SELBOX exhibit an average dynamic power consumption of 0.0026 µW less than that of the BULK structure. This value cannot be ignored when a chip operates using thousands or millions of SOI or SELBOX MOSFETs.

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

Study on the Thermal Conductivity Characteristics for Ultra-Thin Body FD SOI MOSFETs Based on Phonon Scattering Mechanisms.

The silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer intensive self-heating effects due to the reduced thermal conductivity of the silicon layer while the feature sizes of devices scale down to the nanometer regime. In this work, analytical models of thermal conductivity considering the self-heating effect (SHE) in ultra-thin body fully depleted (UTB-FD) SOI MOSFETs are presented to investigate the influences of impurity, free and bound electrons, and boundary reflection effects on heat diffusion mechanisms. The thermal conductivities of thin silicon films with different parameters, including temperature, depth, thickness and doping concentration, are discussed in detail. The results show that the thermal dissipation associated with the impurity, the free and bound electrons, and especially the boundary reflection effects varying with position due to phonon scattering, greatly suppressed the heat loss ability of the nanoscale ultra-thin silicon film. The predictive power of the thermal conductivity model is enhanced for devices with sub-10-nm thickness and a heavily doped silicon layer while considering the boundary scattering contribution. The absence of the impurity, the electron or the boundary scattering leads to the unreliability in the model prediction with a small coefficient of determination.

Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET

This paper presents a dual metal trapezoidal recessed channel metal oxide semiconductor field effect transistor (MOSFET) embedded with asymmetric stack gate with linearly graded metal work-function technique to improve the carrier transport efficiency and device switching performance. The analytical model for the proposed asymmetric-linearly graded trapezoidal gate (ASY–LGTG) silicon on insulator (SOI) MOSFET has been developed considering parabolic approximation of 2-D Poisson’s equation. The threshold voltage of the device is extracted using minimum surface potential. The simulation work has been carried out using a Silvaco TCAD tool to validate the results of the analytical model. This grooved structure exhibits the corner effect, which plays a dynamic role in the improvement of the device performance. However, the impact of the corner effect can be controlled by the groove corner angle and doping concentration. We have also investigated the impact of different structural parameters such as negative junction depth (NJD), corner angle, substrate doping and stack gate features (upper oxide permittivity and oxide thickness ratio) on the performance of minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage and device switching characteristics.

Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance

The kink effect in a fully depleted silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is studied and compared with the results for a SOI metal–oxide–semiconductor field-effect transistor (MOSFET) using a model that is calibrated against experimental results available in literature. A technique for eliminating the kink effect is proposed. The structure with a small gap in the buried oxide, known as the selective buried oxide (SELBOX) structure, is capable of reducing the kink effect. The impact of the kink effect on the device performance for different gap positions, thicknesses, and buried oxide thicknesses is examined. A better current–voltage characteristic is obtained for a position of the gap near the source. The effect of varying the temperature and the presence of a uniform trap charge on the kink effect for the SOI TFET, SOI MOSFET, and SELBOX structures is also studied. Various electrical parameters such as the subthreshold swing and ION/IOFF ratio are investigated for the TFET in the presence and absence of uniform trap charge. Although the SELBOX structure can minimize the kink effect, it is still present for such devices with narrow and wider gaps. Therefore, the gap thickness is optimized based on technology computer-aided design (TCAD) simulations. Furthermore, radio frequency (RF)/analog performance parameters such as the transconductance (gm), cutoff frequency (ft), transconductance generation factor (TGF = gm/ID), transconductance frequency product, gain transconductance frequency product, and 1-dB compression point are investigated using TCAD simulations and compared between the SELBOX MOSFET and SELBOX TFET devices.

Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects

The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schrödinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schrödinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schrödinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages.

Reliability improvements in SOI‐like MOSFET with ESD and self‐heating effect

A new structure of N-type Silicon-on-insulator (SOI)-Like Bulk Silicon (N-SL-BS) metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed to improve the reliability of SOI MOSFET mainly with regards to their self-heating effect and electro-static discharge (ESD) events based on two-dimensional numerical simulation. The new device employs p/n-/p + structure on Si, in which the n-layer is made of Si carbide (SiC), a wide bandgap material. The built-in electric field fully depletes the n-SiC layer and forms an SOI-like feature with a p + layer underneath. Simulations are first implemented in self-heating conditions, to investigate their drain current and temperature ramping. More importantly, ESD pulses assuming the human body model are applied to test their response and observe which device was first to fail using an I-V curve and hole current density distribution. Results show that the new device exhibits superior reliability when compared with a traditional SOI MOSFET. The avalanche breakdown voltage improves nearly 33% and the highest temperature of the global device is more than three times lower than that of an SOI MOSFET subjected to ESD pulses with a peak current of 7 mA.

An Analytical Subthreshold Swing Model for fully-depleted MOSFETs with vertical Gaussian profile fabricated on modified silicon-on-insulator wafers

The objective of this study is to present an analytical subthreshold swing model for fully-depleted metal-oxide semiconductor field-effect transistors (MOSFETs) with vertical Gaussian profile fabricated on modified Silicon-on-Insulator (SOI) wafers. Commercial SOI wafers are radiation hardened by Si+ implantation which creates interface traps at buried SiO2/Si interface. Considering that channel potential is affected by non-uniform doping profile combined with process- and radiation-induced traps, the model is derived based on effective conduction path effect. The proposed model is validated by comparing analytical results with numerical simulation data obtained by using commercially available Sentaurus technology computer-aided design. The model agrees well with experimental extractions of irradiated nMOSFETs. This model is believed to be able to provide better physical insight and understanding of total dose irradiated modified SOI MOSFET devices operating in subthreshold regime.

Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Two-dimensional (2D) analytical models for the subthreshold current and␣subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable␣boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

Investigation of temperature-dependent small-signal performances of TB SOI MOSFETs**Project supported by the National Natural Science Foundation of China (No. 61331006) and the National Defense Pre-Research Foundation of China (No. 9140A11040114DZ04152).

This paper investigated the temperature dependence of the cryogenic small-signal ac performances of multi-finger partially depleted (PD) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs), with T-gate body contact (TB) structure. The measurement results show that the cut-off frequency increases from 78 GHz at 300 K to 120 GHz at 77 K and the maximum oscillation frequency increases from 54 GHz at 300 K to 80 GHz at 77 K, and these are mainly due to the effect of negative temperature dependence of threshold voltage and transconductance. By using a simple equivalent circuit model, the temperature-dependent small-signal parameters are discussed in detail. The understanding of cryogenic small-signal performance is beneficial to develop the PD SOI MOSFETs integrated circuits for ultra-low temperature applications.

Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment

This paper describes an experimental comparative study between the silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) implemented with the octagonal gate geometries and their typical rectangular counterparts operating in high-temperature conditions. The 1 ${\mu }\text{m}$ fully depleted SOI complementary metal-oxide semiconductor technology was employed to manufacture the devices. We observe that the octagonal layout style for MOSFETs is capable of maintaining its better electrical performance (for 573 K: a reduction of the leakage drain current of 65%, an increase of 159% in the saturation drain current, and an increase of 175% in the unit voltage gain frequency) in comparison to the standard rectangular counterpart. This happens because the longitudinal corner effect and parallel connection of MOSFETs with different channel lengths effect continue to function at high temperatures. Therefore, the octagonal layout style can be considered as an alternative hardness-by-design approach to boost the electrical performance of n-type SOI MOSFETs in high-temperature environments, without causing any extra burden for any current planar SOI MOSFET manufacturing process.