Silicon-on-insulator Metal-oxide-semiconductor Field-effect Transistors Research Articles

Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment

This paper describes an experimental comparative study between the silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) implemented with the octagonal gate geometries and their typical rectangular counterparts operating in high-temperature conditions. The 1 ${\mu }\text{m}$ fully depleted SOI complementary metal-oxide semiconductor technology was employed to manufacture the devices. We observe that the octagonal layout style for MOSFETs is capable of maintaining its better electrical performance (for 573 K: a reduction of the leakage drain current of 65%, an increase of 159% in the saturation drain current, and an increase of 175% in the unit voltage gain frequency) in comparison to the standard rectangular counterpart. This happens because the longitudinal corner effect and parallel connection of MOSFETs with different channel lengths effect continue to function at high temperatures. Therefore, the octagonal layout style can be considered as an alternative hardness-by-design approach to boost the electrical performance of n-type SOI MOSFETs in high-temperature environments, without causing any extra burden for any current planar SOI MOSFET manufacturing process.

Amended Electric Field Distribution: A Reliable Technique for Electrical Performance Improvement in Nano scale SOI MOSFETs

To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) with an amended electric field in the channel for improved electrical and thermal performance, with an emphasis on current leakage improvement. The amended electric field leads to lower electric field crowding and thereby we assume enhanced reliability, leakage current, gate-induced drain leakage (GIDL), and electron temperature. To modify the electric field distribution, an additional rectangular metal region (RMR) is utilized in the buried oxide of the SOI MOSFET. The location and dimensions of the RMR have been carefully optimized to achieve the best results. The electrical, thermal, and radiofrequency characteristics of the proposed structure were analyzed using two-dimensional (2-D) numerical simulations and compared with the characteristics of the conventional, fully depleted SOI MOSFET (C-SOI). Also, critical short-channel effects (SCEs) such as threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope degradation, hot-carrier effect, GIDL, and leakage power consumption are improved. According to the results obtained, the proposed nano SOI MOSFET is a reliable device, especially for use in low-power and high-temperature applications.

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson’s equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.

Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs

A new analytical model for the subthreshold swing of nanoscale undoped trigate silicon-on-insulator metal---oxide---semiconductor field-effect transistors (MOSFETs) is proposed, based on the channel potential distribution and physical conduction path concept. An analytical model for the potential distribution is obtained by solving the three-dimensional (3-D) Poisson's equation, assuming a parabolic potential distribution between the lateral gates. In addition, mobile charges are considered in the model. The proposed analytical model is investigated and compared with results obtained from 3-D simulations using the ATLAS device simulator and experimental data. It is demonstrated that the analytical model predicts the subthreshold swing with good accuracy for different lengthes, thicknesses, and widths of channel.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

The impact of high-temperature effects is experimentally investigated in the octagonal layout style for planar silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) field-effect transistors (MOSFETs), named OCTO SOI MOSFETs (OSMs), in relation to the hexagonal [diamond SOI MOSFETs (DSMs)] and the standard (rectangular conventional SOI MOSFETs) ones regarding the same bias conditions. The devices were manufactured with a 1- $\mu\mbox{m}$ fully depleted SOI complementary MOS (CMOS) technology. The main experimental findings demonstrate that OSM is capable of keeping active the longitudinal corner effect and the PArallel connection of MOSFET with Different channel Lengths Effect (PAMDLE) in its structure at high-temperature conditions, and consequently, it maintains its remarkably better electrical performance in comparison with the standard SOI MOSFET, mainly its capacity to reduce the leakage drain current, without causing any extra burden to the current planar SOI CMOS technology in relation to DSMs.

Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET

This paper performs an experimental comparative study of the total ionizing dose effects due to the x-ray radiation between the silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) manufactured with octagonal gate geometry and the standard counterpart. Our main focus is on integrated transceivers for wireless communications and smart-power dc/dc converters for mobile electronics, where the transistor is used as the key switching element. It is shown that this innovative layout can reduce the total ionizing dose (TID) effects due to the special characteristics of the OCTO SOI MOSFET bird’s beak regions, where longitudinal electrical field lines in these regions are not parallel to the drain and source regions. Consequently, the parasitic MOSFETs associated with these regions are practically deactivated.

A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric**The author, Pramod Kumar Tiwari, was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology, Ministry of Human Resource and Development, Government of India under Young Scientist Research (Grant No. SB/FTP/ETA-415/2012).

In this paper, a surface potential based threshold voltage model of fully-depleted (FD) recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional (2D) Poisson’s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model’s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters, including the dielectric constant of gate-dielectric material.

Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment

This paper presents an experimental comparative between the Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET) manufactured with the Wave (S gate geometry) and the standard layout (CnM) considering the Total Ionizing Dose (TID) effects. Due to the special characteristics of the bird’s beaks regions of the Wave MOSFET (WnM), this innovative layout proposal for MOSFETs is able to improve the device TID tolerance without add cost to the Complementary MOS (CMOS) manufacturing process. INTRODUCTION The TID effects cause long term damage in the oxide layers of the electronic devices, worsening the electrical performance of the MOSFET [1]. New materials, multiple-gates and three-dimensional (3D) devices are under intense research and development [1], as seen in the International Technology Roadmap for Semiconductor (ITRS) [2], in order to overcome the scaling limits [3-5]. Several efforts have been made to improve the devices radiation hardness, which mainly can be divided in two categories: one is related to the optimization of CMOS manufacturing process with different materials and technologies and the other focus on using non-standard layout for MOSFET. In this context, the innovative Wave nMOSFET [6] can be an alternative to boost the TID tolerance. Therefore, the purpose of this paper is to present an experimental comparative study of the TID effects between the WnM and CnM, considering the main digital parameters (on-state drain current, ION, off-state drain current, IOFF and the ION/IOFF ratio. WAVE LAYOUT DESCRIPTION Figure 1 presents the layout of the WnM. It is possible to observe the gate, the drain and source for the superior and inferior semicircles, the longitudinal electrical field in the channel, and the bird's beak regions (BBR). Observe that the WnM superior semicircle is in internal drain bias configuration (IDBC), while the inferior semicircle is in external drain bias configuration (EDBC), then the longitudinal electric field (LEF) in those semicircles are different, thus it affects the electrical behavior of the parasitic transistors associated to the WnM BBRs, and as a result, the TID effects are different. EXPERIMENTAL DETAILS The WnM and the CnM were exposed to 10 keV X-rays irradiation using a Shimadzu XRD-7000 for cumulative dose of 1.5 Mrad (first dose of 1 Mrad and second dose of 500 krad) at a dose rate of 400 rad/s in biased devices. The “ON” bias was applied, where the gate is at the bias supply voltage (5 V), and the source, drain, and substrate are grounded (0 V). The devices were manufactured by using the 0.35 μm ON Semiconductor conventional (Bulk) manufacturing CMOS process, via MOSIS Educational Program (MEP) [7]. EXPERIMENTAL RESULTS AND DISCUSSIONS Figure 2 illustrates the experimental curves of the WnM and the CnM counterpart (channel length, L, of 2.3 mm) of the logarithm of the drain current normalized [IDS/(W/L)] as a function of the overdrive gate voltage [VGT], for a drain bias (VDS) of 4 V. By analyzing the Fig. 2, the WnM ION is 9.5% higher than the CnM and the IOFF of both devices are similar in pre-radiation. However, after TID of 1.5 Mrad, the CnM IOFF is about 10% higher than the one found in the WnM counterpart. Furthermore, the WnM ION/IOFF ratio is about 30% higher that found in the equivalent CnM. This is because of the different BBR influence of the WnM compared to the CnM counterpart. IDBC has a smaller drain area and higher LEF, the EDBC is the opposite, as a result, the TID effects are different and they affect the digital electrical parameters. CONCLUSION The Wave layout style to be implemented in MOSFETs is an alternative to boost the TID tolerance and digital ICs operating in radioactive environment (space and medical applications), due to its special layout and different BBR characteristic. REFERENCES [1] H. Barnaby, “Total-Ionizing-Dose effects in modern CMOS technologies,” IEEE Trans. Nuc. Sci., vol. 53, no. 6, pp. 3103- 3120, 2006. [2] International Technology Roadmap for Semiconductors. [3] G. K. Celler and S. Cristoloveanu, “Frontiers of silicon on insulator,” J. Appl. Phys., vol. 93, no. 3, pp. 4955, 2003. [4] J.P. Colinge, et al, “Silicon on insulator “gate all around” device,” in Proc. IEDM Tech. Dig., pp. 595, 1990. [5] M. Vinet, et al, “Bonded planar double-metal-gate NMOS transistors down to 10 nm,” IEEE Elec. Devic. Lett., vol. 26, no. 5, pp. 317, 2005. [6] S. Gimenez, “The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications,” ECS Trans., v. 19. pp. 153-158, San Francisco, 2009. [7] MOSIS Service, 2010. Figure 1

Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node

The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal–oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs.

Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector.

Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation.

Analysis of Hole Lifetime in SOI MOSFET Single-Photon Detector

Hole lifetime in the silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) singlephoton detector was evaluated by the analysis of drain current histograms for different light intensities and substrate voltages. It was found that the peaks in the histogram corresponding to the larger number of stored holes grew as the gate bias decreased. This was attributed not to the increased light absorption efficiency or collection efficiency of the photo-generated holes, but to the prolonged hole lifetime presumably caused by the higher transverse electric field inside the body of SOI MOSFET.

A High Figure-of-Merit SOI MOSFET with a Double-Sided Charge Oxide-Trench

A novel silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) with a high figure of merit (FOM) is proposed. The device features a double-sided charge oxide-trench (DCT) and a trench gate extended to the buried oxide. First, the oxide trench causes multiple-dimensional depletion in the drift region, which not only improves the electric field (E-field) strength, but also enhances the reduced surface field effect. Second, self-adaptive charges are collected in the DCT, which enhances the E-field strength of the trench oxide. Third, the oxide trench folds the drift region along the vertical direction, reducing the device cell pitch. Fourth, one side of the DCT regions acts as the body contact of p-well to reduce cell pitch and specific on-resistance (Ron,sp) further. Compared with a trench gate lateral double-diffused MOSFET, the DCT MOSFET increases the breakdown voltage (BV) from 53 V to 158 V at the same cell pitch of 3.5 μm, or reduces the cell pitch by 60% and Ron,sp by 70% at the same BV. The FOM (FOM=BV2/Ron,sp) of the proposed structure is 23 MW/cm2.

Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance

We studied the impact of voltage difference engineering in a silicon-on-insulator metal oxide semiconductor field-effect transistor (SOI-MOSFET) and compared the performance to that of a conventional SOI-MOSFET (C-SOI). Our structure, called a SIG-SOI MOSFET, includes main and side gates with an optimum voltage difference between them. The voltage difference leads to an inverted channel as an electrical drain extension under the side gate. This channel creates a stepped potential distribution along the channel that it cannot be seen in the C-SOI MOSFETs. The voltage difference controls the channel properly and two-dimensional two-carrier device simulations revealed lower threshold voltage variations, larger breakdown voltage, higher voltage gain, lower hot carrier effects, improved drain-induced barrier lowering, lower drain conductance, higher unilateral power gain, and lower leakage current compared to a C-SOI device. Thus, our proposed structure has higher performance than a typical C-SOI structure.

A Low Specific on-Resistance SOI Trench MOSFET with a Non-Depleted Embedded p-Island

A novel silicon-on-insulator (SOI) trench metal-oxide-semiconductor field effect transistor (MOSFET) with a reduced specific on-resistance (Ron,sp) is presented. It features an oxide-filled trench and a non-depleted embedded p-type island (p-SOI). The oxide trench folds the drift region into a U-shape, resulting in a reduction in cell pitch and Ron,sp. The non-depleted p-island is employed to further reduce Ron,sp by increasing the optimized doping concentration of the drift region without deteriorating the breakdown voltage (BV). The simulation results show that the p-SOI decreases the Ron,sp to 10.2mΩ·cm2 from 17.4mΩ·cm2 of the conventional SOI MOSFET at the same BV.

Structural Dependence of Source-and-Drain Series Resistance on Saturation Drain Current for Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

The structural dependence of series-resistance effects on the saturation current is investigated in sub-20 nm metal–oxide–semiconductor field-effect transistors (MOSFETs). For planer bulk, silicon-on-insulator (SOI), and multi gate (MG) MOSFETs, the reduction rate of the saturation current is calculated using an analytical current model in high-performance (HP), low-operating-power (LOP), and low-standby-power (LSTP) technologies. In HP technology, the reduction rates are 29.0, 25.3, and 22.1% for bulk, SOI, and MG MOSFETs, respectively. In LOP technology, the reduction rates are 23.8, 21.5, and 20.7% for bulk, SOI, and MG MOSFETs, respectively. In LSTP technology, the reduction rates are about 17% for all devices. In HP technology, the ratio of the series resistance to the channel resistance is the dominant factor for the reduction rate. In LOP technology, the ratio of the over drive voltage to the supply voltage is the dominant factor. In LSTP technology, both the resistance and voltage ratios are the dominant factors.

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce Ron,sp and maintain a high breakdown voltage (BV). The BV of 233 V and Ron,sp of 4.151 mΩ·cm2 (VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.

Investigation of the Electrical and Thermal Performance of SOI MOSFETs with Modified Channel Engineering

In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature.

SOI MOSFET with an insulator region (IR-SOI): A novel device for reliable nanoscale CMOS circuits

Abstract Device performance in the electronic circuits degrades with elapsed time. Therefore it is important to design a new device to have a reliable performance. In this paper, we present the unique features exhibited by a novel nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) in which the silicon active layer consists of an insulator region (IR-SOI). The high- K dielectric HfO 2 as an insulator material is located in the silicon active layer and drain region. Our simulation results demonstrate that this leads to improve the hot electron reliability of the IR-SOI in comparison with the conventional SOI-MOSFET (C-SOI). The insulator region HfO 2 considerably decreases the electric field in the channel and drain regions. Therefore, the degradation mechanism in the proposed structure is lower than that in the C-SOI structure because of reduction of hot carrier effect (HCE). Also using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the HCE, off current, gate current and gate induced drain leakage (GIDL) which can effect on the reliability of the CMOS devices.

Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications

In this paper, the authors propose novel metal-oxide-semiconductor field-effect transistor (MOSFET) types featuring additional L-shaped counterdoped areas in the source and/or drain regions of silicon-on-insulator (SOI) MOSFETs to reduce drain-induced barrier lowering (DIBL) through the buried oxide (BOX) layer. The L-shaped region in the drain area shields the BOX layer from penetration by the drain electric field, thereby reducing DIBL in the body region. Simulation of the electrical characteristics of these novel MOSFETs demonstrated more remarkable DIBL suppression and subthreshold slope performance in short-channel regions than in conventional SOI MOSFETs. In addition to this suppression, these novel MOSFETs suppress breakdown voltage more effectively than conventional SOI MOSFETs. The authors concluded that the proposed devices are capable of contributing to the scaling of SOI MOSFETs in ultralarge-scale integration circuits.