Silicon-on-insulator Film Research Articles

Influences of buried-oxide interface on inversion-layer mobility in ultra-thin SOI MOSFETs

This paper reports on a study of the inversion-layer mobility in n-channel Si MOSFETs fabricated on a silicon-on-insulator (SOI) substrate. In order to make clear the influences of the buried-oxide interface on the inversion-layer mobility in ultra-thin film SOI transistors, SOI wafers of different quality at the buried-oxide interface were prepared, and the mobility behaviors were compared quantitatively. The transistors with a relatively thick SOI film exhibited the universal relationship between the effective mobility and the effective normal field, regardless of the buried-oxide interface quality. It was found, however, that Coulomb scattering due to charged centers at the backside interface between SOI films and buried oxides has great influence on the effective mobility in the thin SOI thickness region, depending on the buried-oxide interface quality. This means that Coulomb scattering due to charged centers at the buried-oxide interface can degrade the mobility with decreasing SOI thickness, unless the SOI wafer quality at the buried-oxide interface is controlled carefully.

Electron–phonon coupling in degenerate silicon-on-insulator film probed using superconducting Schottky junctions

Energy flow rate in degenerate n-type silicon-on-insulator (SOI) film is studied at low temperatures. The electrons are heated above the lattice temperature by electric field and the electron temperature is measured via semiconductor–superconductor quasiparticle tunneling. The energy flow rate in the system is found to be proportional to T 5, indicating that electron–phonon relaxation rate and electron–phonon phase breaking rate are proportional to T 3. The electron–phonon system in the SOI film is in the “dirty limit” where the electron mean free path is smaller than the inverse of the thermal phonon wave vector.

Silicon single-electron tunneling device fabricated in an undulated ultrathin silicon-on-insulator film

We report on a silicon single-electron tunneling device fabricated in an ultrathin (∼3 nm) silicon-on-insulator (SOI) film whose surface is undulated by an alkaline-based solution. The nanometer-scaled undulation in the ultrathin film results in great SOI thickness variations and brings about large electron-potential fluctuations, due to the difference of the quantum confinement effects from one part to another. Consequently, a number of quantum dots are effectively formed in the undulated ultrathin SOI film. This device shows clear Coulomb blockade oscillations at 80 K, as well as nonvolatile single-electron memory functions even at room temperature. The measurements of the undulation with atomic force microscopy reveal that the undulation has two correlation lengths. Based on the analysis of electrical characteristics, it is concluded that the Coulomb blockade oscillations are dominated by a quantum dot formed by the longer-correlation-length undulation and that single-electron memory effects are due to quantum dots formed by the shorter-correlation-length undulation.

Hall effect measurements in double-gate SOI MOSFETs

The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall effect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on I D/( g m) 0.5 provides acceptable values for the drift mobility. The experiment reveals high carrier mobility dominated at room temperature by a phonons scattering mechanism and at low temperature by mixed scattering processes, with a predominance of the surface roughness scattering mechanism. No evidence was found for special transport mechanisms induced by volume inversion in relatively thick SOI films.

Efficient electronic cooling in heavily doped silicon by quasiparticle tunneling

Cooling of electrons in a heavily doped silicon by quasiparticle tunneling using a superconductor–semiconductor–superconductor double-Schottky-junction structure is demonstrated at low temperatures. In this work, we use Al as the superconductor and thin silicon-on-insulator (SOI) film as the semiconductor. The electron–phonon coupling is measured for the SOI film and the low value of the coupling is shown to be the origin of the observed significant cooling effect.

Defect transformation study in silicon-on-insulator structures by high-resolution X-Ray diffraction

Silicon-on-insulator (SOI) structures were fabricated by bonding using a new variant of Smart-Cut technology. As-bonded SOI structures are annealed at high temperature (1100°C) for removal of hydrogen, radiation defects and stresses at the bonding interface. The transformation of structural parameters in as-bonded and annealed SOI structures was investigated by high-resolution X-ray diffraction. The large strain observed for as-bonded SOI structures is relaxed during annealing at high temperature and final SOI wafer has strain-free top silicon layer due to defect annealing and viscous flow of SiO2. FWHM value for SOI film is higher than that for typical silicon single crystal and is caused by mosaic-like structure only.

Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide.

Characterization & Analysis of Sub-Grain Boundaries in Sequential Lateral Solidification Processed SOI Films

AbstractThe nature of the formation of sub-grain boundaries within sequential lateral solidification (SLS) processed thin silicon films has been examined using single crystal Si films as a pre- cursor material. Experimental details include the use of an excimer laser projection system and straight-slit beamlets to produce directionally solidified microstructures. Within the SLS processed silicon-on-insulator (SOI) films, three microstructurally distinct regions are identi-fied: (1) an initial planar defect-free area (the extent of which can depend on laser fluence and orientation); (2) a transitional area within which the sub-grain boundaries appear and propagate in a well-defined direction relative to the crystallographic orientation; and (3) a final area characterized by sub-grain boundaries aligning approximately to the scan direction, and the in-plane texture becoming more random. We discuss the results within the context of a plastic deformation model of sub-grain boundary formation.

Silicon quantum point contact with aluminum gate

Fabrication and electrical properties of silicon quantum point contacts are reported. The devices are fabricated on bonded silicon on insulator (SOI) wafers by combining CMOS process steps and e-beam lithography. Mobility of 9000 cm 2 Vs −1 is measured for a 60 nm-thick SOI film at 10 K. Weak localization data is used to estimate the phase coherence length at 4.2 K The point contacts show step like behaviour in linear response conductance at 1.5 K. At 200 mK universal conductance fluctuations begin to dominate the conductance curve. The effective diameter of quantum point constrictions of the devices are estimated to be 30–40 nm. This estimate is based on TEM analysis of test structures and AFM images of the actual device.

Characterization of the silicon on insulator film in bonded wafers by high resolution x-ray diffraction

High resolution x-ray diffraction (HRXRD) is proposed as a nondestructive tool for the characterization of the silicon on insulator (SOI) film in bonded wafers. Although the bonded stack may consist of many amorphous layers, the measured diffraction spectra only show the crystalline SOI layer, thus providing a direct measurement of the film. We have demonstrated that HRXRD is capable of accurately measuring the film thickness, the tilt of the film planes with respect to the substrate planes, and the rotation misalignment of the bonded film with respect to the carrier substrate. SOI films with thicknesses down to 30 nm were readily measured with accuracy better than 1%. It is shown that an angular separation between the layer and the substrate diffraction peaks is maintained due to an unintentional miscut which usually exists in the starting wafers used for bonding. This angular separation is unique to bonded wafers as opposed to separation by implanted oxygen (SIMOX) wafers where the layer and substrate peaks are nonseparable. Calculated diffraction spectra based on the kinematic approach showed excellent agreement with the measured diffraction.

Thickness uniformity of silicon-on-insulator fabricated by plasma immersion ion implantation and ion cut

Plasma immersion ion implantation (PIII) is an economical means to implant a high dose of hydrogen into silicon and when combined with ion cut, has been demonstrated to be a viable technique to fabricate silicon-on-insulator (SOI). However, its success in the industry hinges on the quality of the SOI wafers produced. One of the most important parameters is the thickness uniformity of the SOI film. We have observed that the thickness variation across a 150 mm wafer follows a pattern in which the transferred silicon film is thickest in the center and thinnest near the edge. Alpha step and SIMS measurements indicate that the lateral nonuniformity is caused by the different penetration depths of hydrogen across the wafer. The experimental results can be explained quantitatively by an oblique incidence model.

High-temperature characteristics of zone-melting recrystallized silicon-on-insulator MOSFETs

The characteristics of enhancement-mode MOS transistors fabricated on zone-melting recrystallized (ZMR) silicon-on-insulator (SOI) films were systematically experimentally investigated in the temperature range 25–300°C. The main temperature-dependent parameters (the threshold voltage, the channel mobility, subthreshold slope, off-state leakage currents) of ZMR SOI MOSFETs are described and compared with both theory and SIMOX devices. It is shown that high carrier mobilities and low off-state leakage currents can be obtained in thin-film ZMR SOI MOSFETs at elevated temperatures. At T = 300°C, far beyond the operating range of bulk silicon devices, the off-state leakage current in ZMR SOI MOSFETs with a 0.15 mm-thick silicon film was only 0.5 nA/mm (for VD = 3 V), that is 3–4 orders of magnitude lower than typical values in bulk Si devices. The presented results demonstrate that CMOS devices fabricated on sufficiently thin ZMR SOI films are well suited for high-temperature applications.

High-current small-parasitic-capacitance MOSFET on a poly-Si interlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO/sub 2/. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO/sub 2//poly-Si/500-nm SiO/sub 2/) wafer. In this device, the highly concentrated p/sup +/ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages.

Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (/spl sim/450/spl deg/C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p/sup +/SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented.

Mobility Enhancement of SOI MOSFETs due to Subband Modulation in Ultrathin SOI Films

We propose that silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs) with SOI films thinner than the inversion layer of the bulk MOSFETs can provide higher inversion-layer mobility than the bulk Si MOSFETs, because of the significant modulation of the subband structure due to the size effect of the ultrathin SOI films. In order to examine the effectiveness of this device structure on the mobility enhancement, a theoretical calculation of the inversion-layer mobility at room temperature is performed. It is found that the mobility of the SOI MOSFETs with a SOI thickness of around 3 nm can be higher than that of the bulk MOSFETs. This mobility enhancement is attributed to an increase in the occupancy of the 2-fold valleys and the suppression of inter-valley phonon scattering, associated with the energy splitting between the 2-fold and the 4-fold valleys due to the size effect of the SOI films.

EBIC investigation of defects in SOI materials using a Schottky diode and buried oxide capacitor

Silicon-on-insulator (SOI) is a promising technology for the fabrication of ultra large scale integration circuits as thin silicon layers of good crystalline quality are now available which permit substantial enhancements of device performance. However, the fabrication of ultra thin films suitable for CMOS applications often reveals some crystal defects which must be characterised to understand their consequences on device performances. Such defects were already extensively studied from a crystal point of view using preferential etching techniques. In this work, the non-destructive electron beam induced conductivity (EBIC) technique was successfully used to study dislocations and stacking faults in SOI films obtained by direct bonding. The presence of a buried oxide in the SOI structure prevented any direct current path between the collection junction formed on the active layer and the back ohmic contact. It is shown that collection using a Schottky junction in series with the buried oxide capacitor yields a differentiation of the EBIC signal. The latter may be digitally integrated to retrieve the image with a substantially improved signal over noise ( S/N) ratio. The variation of the EBIC signal as a function of the scanning rate was also investigated. This technique permitted the observation of stacking faults and dislocations in the active layer simultaneously with defects in the buried oxide and/or at the silicon-oxide interface.

Modeling of anomalous current-voltage characteristics in floating body fully depleted SOI nMOSFETs

An analytic model is derived for predicting the anomalous I D− V GfS and I D− V DS characteristics in a floating body fully depleted silicon-on-insulator (SOI) nMOSFETs with parasitic bipolar junction transistor (BJT). All current components in the MOSFET as well as the parasitic BJT are considered in this model. It shows that the single-transistor latch in the I D− V GfS characteristics is due to multistable floating body potentials. The study also reveals that the breakdown and latch phenomena are strongly dependent on the parasitic bipolar current gain and multiplication factor. The effective mobility variation and short channel effects are included in this model. Furthermore parametric dependences, such as SOI film thickness and body doping concentration, are examined to alleviate the latch effect and give the physical insight for optimal design. Results obtained from this model are in good agreement with the measured I D− V GfS and I D− V DS characteristics.

Double-charge-sheet model for thin silicon-on-insulator films

A simple algorithm is proposed that facilitates the calculation of surface potentials and charge densities at the front and back interfaces in thin silicon-on-insulator (SOI) layers by decoupling of the potentials and charges at the two interfaces. An expression relating the front surface potential and inversion charge to the front and back gate biases is derived and compared with a numerical solution of Poisson's equation. The charge-sheet model agrees well with the simulation results over the front-surface bias range from weak to heavy inversion and with the back silicon surface biased into accumulation, depletion, and inversion. The results are shown to be reasonably accurate for all doping densities of common interest and for SOI film thicknesses above approximately 20 nm. An extension of the model to a nonequilibrium system is used to derive an expression for the drain current in a fully-depleted SOI MOSFET. Other applications of the model include a closed-form analytical solution for the threshold voltage and a calculation of the interface-state trapped charge.

Numerical Simulation of Silicon-on-Insulator Thin-Film Solar Cells

The properties of thin-film single-crystalline silicon solar cells fabricated on silicon-on-insulator (SOI) substrate have been investigated through two-dimensional numerical device simulation. The SOI film/buried SiO2 interface condition is changed by varying the back-gate bias. When carriers are caused to accumulate the bottom region of the SOI film by application of large back-gate bias, the conversion efficiency is improved compared to that at zero back-gate bias. However, sufficiently high conversion efficiency cannot be obtained using the conventional structure. One proposal to increase the conversion efficiency of SOI thin-film solar cells is to form a very heavily doped region in the bottom of the SOI film. The newly proposed SOI solar cell has a conversion efficiency of about 24% if complete optical confinement is assumed.

Measurements of the Breakdown Voltage of the Lateral Insulated Gate Bipolar Transistor on the Silicon-on-Insulator Film with Varying Implantation Doses for the N-Buffer Layer

The blocking capability of the lateral insulated gate bipolar transistor (LIGBT) fabricated on the silicon-on-insulator (SOI) film is investigated experimentally with varying implantation doses for the n-buffer layer. This note shows the experimental results on the breakdown voltage at room temperature and 125° C. The blocking capability of the LIGBT on the SOI film depends strongly on the implantation dose for the n-buffer layer.