Silicon Nanowire MOSFETs Research Articles

Coupled Mechanical and 3-D Monte Carlo Simulation of Silicon Nanowire MOSFETs

In this paper we report on a general methodology to investigate nanowire MOSFETs based on the coupling of mechanical simulation with 3-D real-space Monte Carlo simulation. The Monte Carlo transport model accounts for both strain silicon and quantum mechanical effects. Mechanical strain effects are accounted for through an appropriate change of the anisotropic band structure computed with the empirical pseudopotential method. Quantum effects are instead included by means of a quantum mechanical correction of the potential coming from the self-consistent solution of the Schrodinger equation. This methodology has been then applied to the simulation of a test case silicon nanowire n-MOSFET. Impact of mechanical strain and quantum effects on the drive current is investigated. It is shown that only the inclusion of strain and quantum mechanical effects allows a good agreement with experimental data, demonstrating the validity of the proposed methodology for ultimate devices.

Transport in Ultrathin SOI MOSFETs and Silicon Nanowire Transistors

Transport in ultra-thin-body (UTB) SOI MOSFETs and silicon nanowire MOSFETs is extensively studied by experiments and calculations. The transport properties in these devices are strongly affected by the quantum confinement effects. Mobility enhancement of both electron and hole is experimentally demonstrated in (110) UTB SOI MOSFETs. The characteristic variations of silicon nanowire transistors with nanowire width of less than 10 nm are also experimentally investigated.

Present and Future of Si-Based Transistor Technology for Memories

Nanotechnology is named as a promising research area for the semiconductor technology to be extended or replaced by it. Since the silicon based devices such as NAND Flash memory, DRAM, SRAM, and CPUs are scaled down below 100 nm entering into the nanoscale regime late 1990s, in the middle of 2005, we are already facing the appearance of sub 50 nm technology in production. In this paper, we introduce recent technology development activities in Samsung to realize the sub 50 nm technologies into the devices such as SRAM, DRAM, and Flash memories as well as the high performance logic devices. RCAT (Recessed Cell Array Transistor), PiFET (Partially-insulated MOSFET) and FinFET, McFET (Multi channel FET), MBCFET (Multi- Bridge Channel MOSFET), and Twin Silicon Nanowire MOSFET (TSNWFET) are the 3-dimensional structure CMOS transistors to be introduced for nanoscale applications.

Influence of band structure on electron ballistic transport in silicon nanowire MOSFET’s: An atomistic study

This work investigates the conduction band structure of silicon nanowires, its dependence with the wire width and its influences on the electrical performances of Si nanowire-based MOSFET’s working in the ballistic regime. The energy dispersions relations for Si nanowires have been calculated using a sp 3 tight-binding model and the ballistic response of n-channel devices with a 3D Poisson–Schrödinger solver considering a mode-space approach and open boundary conditions (NEGF formalism). Results are compared with data obtained considering the parabolic bulk effective mass approximation, highlighting in this last case the overestimation of the I on current, up to 60% for the smallest (1.36 nm × 1.36 nm Si wire) devices.

Compact modeling of the threshold voltage in silicon nanowire MOSFET including 2D-quantum confinement effects

A quantum-mechanical compact model of the threshold voltage (V T) for quantum nanowire MOSFETs has been developed. This approach is based on analytical solutions for the decoupled 2D Schrödinger and 1D Poisson equations solved in the silicon channel. A quantum correction based on the perturbation theory has been also introduced to improve the model accuracy. Finally, the validity of the model has been verified by comparison with data obtained with a 2D/3D Poisson-Schrödinger drift-diffusion simulation code.