Junctionless Silicon Nanowire Research Articles

Transport spectroscopy from Hubbard bands of dopant-induced quantum dot array to one-dimensional conduction subband

Arrays of dopant-induced quantum dots (QDs) are promising candidates as quantum bit platforms. We have achieved quantum transport spectroscopy of a junctionless silicon (Si) nanowire transistor with dual physical channels with a diameter of 10 nm fabricated by novel femtosecond laser projection exposure together with thermal oxidation. The spectroscopy demonstrates the evolution of the quantum transport process from Hubbard bands of dopant-induced QD array to one-dimensional (1D) conduction subbands. Eight pairs of current splitting peaks were observed at the initial stage of the drain current, representing the upper and lower Hubbard bands formed by the coupling of eight QDs. The current oscillation peaks in the 1D conduction subband elucidate the interference of reflected electron waves between the gate-defined barriers, which are proved by the mean wave vector interval matching the gate length. Our experimental results demonstrate the evolution of the quantum transport process in sub 10 nm dual Si channels with randomly doped dopant atoms, opening a new perspective for quantum states by dopant band engineering in Si nanoscale devices for scalable quantum computation.

Numerical assessment of high-k spacer on symmetric S/D underlap GAA junctionless accumulation mode silicon nanowire MOSFET for RFIC design

In this work, inclusion of high-k spacer on symmetric underlap S/D junctionless silicon nanowire (SiNW) MOSFET is studied with an aim to analyze more realistic estimation of device performance in sub-20 nm. Comparison made with junctionless silicon nanowire shows that underlap high-k spacer significantly reduces off-current (≈ 64 mV/decade) and achieves high switching ratio > 109 due to fringing field which tends to increase effective channel length. Variation of different high-k spacer values (k = 3.9, 9.1, 11, 25, and 40) is examined and following static and Analog/RF performance is studied: potential, electric field, band diagram, transconductance, device efficiency, quality factor, capacitances, cutoff frequency (fT), intrinsic delay (τ), TFP, EDP, and GBP. It is observed that for high k = 40 (TiO2), device performance of junctionless SiNW MOSFET improves noticeably in comparison to low-k value. In addition, variation of S/D underlap spacer length (Lsp) along with spacer dielectric has also been done and results reveal that TiO2 with 10 nm spacer length is optimum value for upgraded analog/RF performance. Thus, symmetric S/D underlap junctionless SiNW MOSFET can be considered as a promising component in low-power switching component in RFIC circuits.

Room temperature terahertz detector based on single silicon nanowire junctionless transistor with high detectivity

In this work, the n-type single silicon nanowire (NW) based junctionless field-effect transistor (FET) is demonstrated as an efficient terahertz (THz) detector. For the effective coupling of the THz radiations with NW junctionless FET, the lobes of the rounded bow-tie antenna are connected to the gate and source terminals of the device. The antenna design is optimized with proper impedance matching conditions to achieve maximum power transfer between antenna and detector. The simulated antenna resonates at 0.43 THz frequency with 19 GHz bandwidth. Further simulations have been done on Lumerical finite difference time domain software to analyze the electric field distribution profile. To investigate the optical response of this optimized antenna design, an array of the simulated antenna has been fabricated and its transmission spectra are measured. Finally, the simulated antenna has been integrated with the n-type NW junctionless transistor. A maximum responsivity of 468 V W−1 at 0.425 THz frequency and noise-equivalent-power of ∼ 10−9W/Hz1/2 is obtained at room temperature. The complementary metal-oxide-semiconductor’s compatibility, ease of integration on chips, possibility to realize multiple pixel arrays, andscalability to higher frequencies, make this device promising for THz electronics.

Junctionless Silicon Nanotube TFET for Improved DC and Radio Frequency Performance

In this work, a junctionless silicon nanotube TFET (JL-SiNT-TFET) is reported for low standby power and high-frequency applications. The workfunction of the core gate (CG) metal is considered similar to the outer gate electrode. The length of the CG is extended up to the source region and connected to the gate supply voltage. The inclusion of the CG offers better electrostatic controllability and enables a steep turn on capability. While maintaining low IOFF and targeting the optimum performance of the device, the JL-SiNT-TFET shows 19.8 mV/dec subthreshold swing (SS), ultra-low OFF-state leakage current, higher drive current as compared to the junctionless silicon nanowire TFET (JL-SiNW-TFET). However, temperature and substrate doping effect on device performance, core gate position optimization, the impact of channel length variation on SS, ION/IOFF ratio, and RF parameters are also investigated for choosing the most favorable values.

Simulation on Junctionless Silicon Nanowire Devices for Implementation of Photodetection Circuit in Retinal Prosthesis

Simulation on Junctionless Silicon Nanowire Devices for Implementation of Photodetection Circuit in Retinal Prosthesis

Demonstration of Thermally-Assisted Programming With High Speed and Improved Reliability for Junctionless Nanowire NOR Flash Memory

This study demonstrated the thermally-assisted (TA) programming of a NOR flash memory device, which was composed of a junctionless silicon nanowire with gate-all-around structure. Fast programming was achieved with the aid of Joule heat, which was generated in a homogeneously heavily doped SiNW by a voltage difference between the source and drain. Its programming speed is the fastest among various NOR flash memories ever reported. The mechanism for programming NOR flash memory inevitably degrades the quality of the tunneling oxide. But the proposed thermally-assisted programming provides simultaneous curing of the damaged tunneling oxide.

Experimental and Simulation Study of Silicon Nanowire Transistors Using Heavily Doped Channels

The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for 1.8 V gate overdrive with an off-current set at 100 nA/μm. On- to off-current ratios above 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> with a subthreshold slope of 66 mV/dec are demonstrated at 25 °C. Simulations using drift-diffusion which include density-gradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength.

Trap studies in silicon nanowire junctionless transistors using low-frequency noise

A method to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. JLTs are fabricated in a bottom-up fabrication technique using in situ highly doped nanowires grown by low pressure chemical vapor deposition. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f noise depending on the gate bias. Analysis of the results indicates very low trap densities in the order of 1016 cm−3eV−1. Low trap densities in these devices are associated with their simple fabrication technique, in situ oxide formation, and the absence of semiconductor junction and the ion implantation step in the process. A simple analysis of the low-frequency noise data leads to the density of the traps and their energy within the semiconductor bandgap and their location from the Si/SiO2 interface.

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The proposed method uses the subthreshold slope extraction combined with the substrate bias in order to induce a variation in the channel potential, such that the interface trap density can be extracted for a significant energy range. Three-dimensional TCAD numerical simulations have been performed to analyze the accuracy of the proposed method considering different concentrations and trap density profiles (uniform and exponential). The influence of the device width variation on the trap energy determination has been analyzed, showing that only for positive substrate biases the energy might be affected. The method precision was also analyzed, showing that the trap density extraction is only effectively affected for low Nit values, which do not influence significantly the device performance. Finally, the method has been applied to experimental transistors with high-κ and silicon dioxide gate dielectrics showing consistent results.

Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor

Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor

A surface‐potential‐based model for silicon nanowire junctionless field‐effect transistors including interface traps

SUMMARYInterface trap is directly related to the electrical characteristics and reliability of the transistor, and it is an important factor affecting the performance of the device. This paper presents an analytic surface‐potential‐based model for cylindrical silicon nanowire junctionless field‐effect transistors (Si‐NW JLFET) including interface traps. In this paper, the proposed model is applicable to all Si‐NW JLFET working region including different interface trap charges with several nanowire radii and doping concentrations. Simulation results show that interface trap charges present two properties (positive or negative) depending on the different positions of the Fermi level in band gap, which have a significantly influence on the surface potential to cause junctionless transistor subthreshold degradation and flatband shifting. In addition, appropriate device parameters can effectively reduce the impact to the characteristic of the device made by the interface trap without degrading the performance of device. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Mixed-Mode Analysis of Different Mode Silicon Nanowire Transistors-Based Inverter

In this paper, we focused on the comparison and analysis of the performance of inversion-mode (IM), accumulation-mode (AM), and junctionless (JL) silicon nanowire field-effect transistors (NWTs)-based inverter. The effects of the radius, equivalent oxide thickness and source/drain doping in the different mode nanowire device structure are investigated. The capacitance components and transient characteristics, which determine the behavior of devices in the circuits, are studied and compared among different mode nanowire devices. The mixed-mode circuit simulations have been performed for the inverter circuit and three-stage ring oscillator consist of n-type and p-type IM/AM/JL NWTs. JL NWTs show lower Miller capacitance which contributes to suppressing the overshoot effect in the circuits. Results of these simulations can give insights into the in-circuit behavior of these future generation devices.

Pinch-Off Effect in P-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Nanolithography

The spark of aggressive scaling of transistors was started after the Moors law on prediction of device dimensions. Recently, among the several types of transistors, junctionless transistors were considered as one of the promising alternative for new generation of nanotransistors. In this work, we investigate the pinch-offeffect in double gate and single gate junctionless lateral gate transistors. The transistors are fabricated on lightly doped (1015) p-type Silicon-on-insulator wafer by using an atomic force microscopy nanolithography technique. The transistors are normallyonstate devices and working in depletion mode. The behavior of the devices confirms the normal behavior of the junctionless transistors. The pinch-offeffect appears at VG+2.0 V and VG+2.5 V for fabricated double gate and single structure, respectively.Onstate current is in the order of 10-9(A) for both structures due to low doping concentration. The single gate and double gate devices exhibit anIon/Ioffof approximately 105and 106, respectively.

Junctionless silicon nanowire transistors for the tunable operation of a highly sensitive, low power sensor

Silicon nanowire (SiNW) field effect transistors (FETs) have been widely investigated as biological sensors for their remarkable sensitivity due to their large surface to volume ratio (S/V) and high selectivity towards a myriad of analytes through functionalization. In this work, we propose a long channel (L>500nm) junctionless nanowire transistor (JNT) SiNW sensor based on a highly doped, ultrathin body field-effect transistor with an organic gate dielectric εr=1.7. The operation regime (threshold voltage Vth) and electrical characteristics of JNTs can be directly tuned by the careful design of the NW/Fin FET. JNTs are investigated through 3D Technology Computer Aided Design (TCAD) simulations performed as a function of geometrical dimensions and channel doping concentration Nd for a p-type tri-gated structure. Two different materials, namely, an oxide and an organic monolayer, with varying dielectric constants εr provide surface passivation. Mildly doped Nd=1×1019cm−3, thin bodied structures (fin width Fw<20nm) with an organic dielectric (εr=1.7) were found to have promising electrical characteristics for FET sensor structures such as Vth~0V, high relative sensitivities in the subthreshold regime S>95%, high transconductance values at threshold gm,Vfg=0V>10nS, low subthreshold slopes SS~60mV/dec, high saturation currents Id,max~1–10μA and high Ion/Ioff>104–1010 ratios. Our results provide useful guidelines for the design of junctionless FET nanowire sensors that can be integrated into miniaturized, low power biosensing systems.

A Junctionless Gate-All-Around Silicon Nanowire FET of High Linearity and Its Potential Applications

The linearity of a gate-all-around junctionless silicon nanowire (SiNW) FET has been analyzed. The SiNW FET shows a perfectly linear <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$I_{D}$</tex></formula> – <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{G}$</tex></formula> relation and a nearly zero output conductance. The mechanism of its linear behaviors due to degenerate doping level has been also demonstrated. For RF applications, the proposed SiNW FET exhibits a much lower distortion for a whole range of load resistance, making it superior to modern short-channel MOSFET.

First Principle-Based Analysis of Single-Walled Carbon Nanotube and Silicon Nanowire Junctionless Transistors

Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction, and thus, can be easier to implement in aggressive geometries. In this paper, we explore a similar architecture for aggressively scaled devices with the channel consisting of doped carbon nanotubes (CNTs). Gate all around field effect transistor (FET) structures are investigated for n- and p- type doping. Current-voltage characteristics and subthreshold characteristics for a CNT-based junctionless FET is compared with a junctionless silicon nanowire FET with comparable dimensions. Despite the higher on-current of the CNT channels, the device characteristics are poorer compared to the silicon devices due to the smaller CNT bandgap.

Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode.

The piezoresistive effect in n-type junctionless silicon nanowire transistors

The piezoresistive effect in n-type silicon nanowires on silicon-on-insulator wafers, also called junctionless nanowire transistors (JNTs), is investigated. A marked change in the subthreshold drain current for strained JNTs is observed. This change can be attributed to strain-induced interface state modification, due to an increase in the interface state for tensile strain or a decrease in the trap activation energy for compressive strain. Through many long-time cycles of compressive and released strain, the electromechanical response of subthreshold IDS with time is found, thus supporting the widely reported giant piezoresistance effect. In addition, JNTs involving a back-gate and an additional top-gate electrode may become a new prospect for high-precision sensor applications and next-generation multigate transistors.

Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography

The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.

Extraction Method for Substrate-Related Components of Vertical Junctionless Silicon Nanowire Field-Effect Transistors and Its Verification on Radio Frequency Characteristics

Extraction Method for Substrate-Related Components of Vertical Junctionless Silicon Nanowire Field-Effect Transistors and Its Verification on Radio Frequency Characteristics