Numerical assessment of high-k spacer on symmetric S/D underlap GAA junctionless accumulation mode silicon nanowire MOSFET for RFIC design

Abstract

In this work, inclusion of high-k spacer on symmetric underlap S/D junctionless silicon nanowire (SiNW) MOSFET is studied with an aim to analyze more realistic estimation of device performance in sub-20 nm. Comparison made with junctionless silicon nanowire shows that underlap high-k spacer significantly reduces off-current (≈ 64 mV/decade) and achieves high switching ratio > 109 due to fringing field which tends to increase effective channel length. Variation of different high-k spacer values (k = 3.9, 9.1, 11, 25, and 40) is examined and following static and Analog/RF performance is studied: potential, electric field, band diagram, transconductance, device efficiency, quality factor, capacitances, cutoff frequency (fT), intrinsic delay (τ), TFP, EDP, and GBP. It is observed that for high k = 40 (TiO2), device performance of junctionless SiNW MOSFET improves noticeably in comparison to low-k value. In addition, variation of S/D underlap spacer length (Lsp) along with spacer dielectric has also been done and results reveal that TiO2 with 10 nm spacer length is optimum value for upgraded analog/RF performance. Thus, symmetric S/D underlap junctionless SiNW MOSFET can be considered as a promising component in low-power switching component in RFIC circuits.