6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Yi-Bo Liao Yi-Bo Liao,Meng-Hsueh Chiang Meng-Hsueh Chiang,Wei-Chou Hsu Wei-Chou Hsu,N Damrongplasit,Tsu-Jae King Liu

doi:10.1109/vlsi-tsa.2013.6545631

6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Yi-Bo Liao Yi-Bo Liao, Meng-Hsueh Chiang Meng-Hsueh Chiang + Show 3 more

https://doi.org/10.1109/vlsi-tsa.2013.6545631

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Publication Date: Apr 1, 2013

Citations: 6

Affiliation: National Ilan University, National Cheng Kung University, University of California, Berkeley

#Silicon Nanowire MOSFETs #SRAM Cell Design + Show 8 more

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Abstract

6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.

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