Silicon IC Processing Research Articles

Analysis and Design of a High-Coupling-Factor Marchand-Balun Variant Suitable for Standard Silicon IC Process and Its Wide-Band Gilbert Mixer Application

Analysis and Design of a High-Coupling-Factor Marchand-Balun Variant Suitable for Standard Silicon IC Process and Its Wide-Band Gilbert Mixer Application

A fully functionalized metamaterial perfect absorber with simple design and implementation.

Broadband perfect metamaterial absorbers have been drawing significant attention in recent years. A close-to-unity absorption over a broad spectral range is established and this facilitates many photonic applications. A more challenging goal is to construct a broadband absorber with a tailored spectral absorption. The spectral absorption control and spectral shaping are very critical in many applications, such as thermal-photovoltaic, thermal emitters, spectrum imaging system, biomedical and extraterrestrial sensing, and refractive index sensor. In this work, one-dimensional (1D) planar stacking structure is designed to achieve the ultimate goal of a functionalized absorber with a fully tailorable spectral absorption. The lithography and etching process are totally eliminated in this proposed structure, and the fabrication is fully compatible with the regular silicon IC processing. By using ~2 nm ultra-thin metallic layers with a 10-pair (10X) SiO2/Si3N4 integrated dielectric filter, we can achieve decent spectral response shaping. The planar configuration of the ultra-thin-metal metamaterial perfect absorber (MPA) is the key to the easy design/integration of the dielectric filters on top of the MPA. Specifically, band-rejected, high-pass, low-pass and band-pass structure are constructed successfully. Finally, experimental evidence to support our simulation result is also provided, which proves the feasibility of our proposal.

A High Power Driver IC for Electroluminescent Panel: Design Challenges and Advantages of using the Emerging LEES-SMART GaN-on-CMOS process

The Electroluminescent (EL) panel is an emerging backplane lighting technology and becoming increasingly popular in advertising display and facade decoration. Despite the increased popularity of the EL panel, driver circuit for large EL panel is nascent in part because of the required high output power. In this paper, a novel high power EL driver IC based on the emerging LEES-SMART GaN-on-CMOS process are presented and we show that this integrated class-D EL driver is advantageous compared to EL driver IC based on state-of-the-art silicon IC process.

실리콘 애벌런치 LED의 설계요소에 대한 분석

반도체 소자의 축소로 인한 처리속도의 향상이 더욱 어려워지고 있다. 따라서 반도체 산업의 새로운 도약을 위해서 실리콘을 이용한 광전소자의 출현(Silicon photonics)이 더욱 절실해지고 있다. 제조의 간단성, 반복성, 안정성, 고속성, 일반실리콘 반도체 공정과의 병존성 등의 특성으로 인해 애벌런치 항복에 의한 발광 소자는 실리콘 발광소자의 구현에 유력한 후보 중의 하나이다. 애벌런치 발광현상에 대해 전기적, 광학적 측정을 하고, 간단한 모델링과 시뮬레이션을 통하여 발광부위의 형태, <TEX>$n^{+}-p$</TEX> 접합의 깊이, 불순물의 농도, 에피층의 높이 등의 설계요소가 발광특성에 미치는 영향을 분석하였다. 시뮬레이션의 결과와 실제의 계측 결과를 비교하여, 차이점을 야기하는 이유, 애벌런치 항복의 발광현상을 설명하였고, 개선방안을 제시하였다. It is becoming more difficult to improve the device operating speed by shrinking the size of semiconductor devices. Therefore, for a new leap forward in the semiconductor industry, the advent of silicon opto-electronic devices, i.e., silicon photonics is more desperate. Silicon Avalanche LED is one of the prospective candidates to realize the practical silicon opto-electronic devices due to its simplicity of fabrication, repeatability, stability, high speed operation, and compatibility with silicon IC processing. We conducted the measurement of the electrical characteristics and the observation of the light-emitting phenomena using optical microscopy. We analyzed the influence of the design elements such as the shape of the light-emitting area and the depth of the <TEX>$n^{+}-p^{+}$</TEX> junction with simple device modeling and simulation. We compared the results of simulation and the measurement and explained the discrepancy between the results of the simulation and the measurement, and the suggestions for the improvement were given.

Optical contactless probing: an all-silicon, fully optical approach

With decreasing feature size and increasing chip densities, the classical mechanical probe approach for internal fault detection and functional testing faces increasing challenges. Contactless testing might resolve many of the challenges associated with conventional mechanical wafer testing. This article reviews and explains existing optical contactless technologies and introduces a new test methodology - a fully optical contactless testing technique. The proposed method's uniqueness lies in the fact that it is a fully optical technique that uses visible light and is completely compatible with standard silicon IC processing. The technique produces results that demonstrate its feasibility and show its advantages over other optical contactless testing methods.

State-of-the-Art in Integrated Optical Microspectrometers

Microspectrometers fabricated in silicon using microelectromechanical systems technologies are versatile microinstruments: small, lightweight, and featuring a demonstrated capability for spectral analysis. When realized using silicon process compatible technologies, low-cost batch fabrication of an intelligent optoelectronic system-on-a-chip is feasible by cointegration of optics with microelectronic circuits. However, the spectral resolution of devices presented so far has been limited to about R=15, which does restrict application. This paper provides an overview of microspectrometers operating in the visible and infrared spectral range. Moreover, it is demonstrated that the resolution is primarily limited due to the short optical path that is inherent to a microsystem, optical properties of silicon IC-process compatible materials, and lack of adequate optical signal conditioning.

Release of multi-layer metal structure in MEMS devices by dry etching technique

Reactive ion etching technique was used to remove interleave photoresist layer for free standing metal structure in microelectromechanical systems (MEMS) devices. Mixture of oxygen and CF 4 gas was used to get isotropic etching profile. Etching process was optimized to get large metal structure of 100×100 μm 2 without any surface bending. The etching rate of 0.7 μm/min at 60 W of RIE plasma power is found to be optimum process for the particular application. The reported dry release technique is fully compatible with standard silicon IC processing and hence can be used for hybridize process used in MEMS array application.

Compatibility of CO gas sensitive SnO 2/Pt thin film with silicon integrated circuit processing

In this paper, we discuss the integration problems associated with tin dioxide thin film to meet the requirement of silicon IC processing. Since aluminum is being used as interconnection metal lines in various IC devices, the post annealing of tin dioxide thin film cannot be performed at high temperatures. At higher annealing temperature, the aluminum diffuses into the silicon and forms a metal alloy, which reduces the performance of the device. To overcome this problem, we propose an annealing process for the tin dioxide thin film at 450°C in oxygen ambience for shorter time (15 min) and then quenching at room temperature. The performance, such as sensitivity and response time of the quenched device, is better than that of the device cooled at 50°C/h. Sensor measurements were performed at 150–300°C at 400–1000 ppm CO gas concentration, and stability of the devices was measured up to 720 h. The device was stable during long operation hours. Hydrogen gas was used to investigate the selectivity of the device. The response indicated that the quenched device was selective towards CO gas. The response of the quenched device was quite different towards CO and hydrogen gas. The morphology of the devices was investigated using SEM.

Dry release of metal structures in oxygen plasma: process characterization and optimization

A surface micromachining fabrication scheme suitable for fabrication of free-standing metallic structures is presented. The technique is based on using conventional photoresist as a sacrificial layer, on which a metal structural layer is evaporated and patterned. The resulting structures are subsequently dry released in an isotropic oxygen plasma. For the HPR504 and HiPR6517 photoresists, a lateral underetching rate (at a power of 1000 W) of up to 1 was obtained. Structures with lateral dimensions of at least up to can be released as no etch-rate saturation for underetching beyond 20 m was observed. The process has been tested using Al as a structural layer, but any metal that can be evaporated or sputtered can be used. The presented dry-release technique is fully compatible with standard silicon IC processing and can be applied as a post-processing module. The technique eliminates any sticking problem and simplifies processing as compared to wet-etching release.

Silicon IC compatible LIGA mask-fabrication process

This paper describes a technique for fabricating a LIGA mask that offers good compatibility with the silicon IC process. X-ray exposure can be eliminated from the LIGA mask-fabrication process, so that LIGA masks can be fabricated with existing silicon IC process equipment. A gold absorber pattern, 2 μm wide and 10 μm thick, has been successfully fabricated by combining a three-layer resist-patterning process with the electroplating process. Improvements in both the mask structure and fabrication process alleviate the problems of dust in a cleanroom and contamination in the etching chamber.

An integrated optic adiabatic TE/TM mode splitter on silicon

A compact integrated optic fundamental TE/TM mode splitter, based on the mode-sorting characteristics of an asymmetrical adiabatic Y junction of optical waveguides exhibiting shape birefringence, operating at 1550 nm, is designed, using the discrete sine method (DSM) and the beam propagation method (BPM). The structures are fabricated in a system of SiO/sub 2/, SiO/sub x/N/sub y/, and Si/sub 3/N/sub 4/ layers, using a low-temperature plasma-enhanced chemical-vapor deposition (PECVD) process, compatible with standard silicon IC processing. >

A silicon electrostatic ultrasonic transducer

An electric ultrasonic transducer is developed by using a silicon IC process. Design considerations are first presented to obtain high sensitivity and the desired frequency responses in air. The measured transmitter sensitivity is 19.1 dB (0 dB=1 mubar/V) at a point 50 cm away from the devices, when the devices are operated at 150 kHz. The receiving sensitivity is 0.47 mV/Pa in the 10-130-kHz range, with bias voltages as low as 30 V. An electronic sector scanning operation is also achieved by time-sequentially driving seven elements arranged in a linear array on the same chip. The results should be helpful in the design of phased-array transducers integrated with electronic scanning circuits.

ChemInform Abstract: PHOTO‐CVD FOR VLSI ISOLATION

This paper reviews the technique of photochemical-assisted vapor deposition (photo-CVD), and its applications in silicon IC processing. The photo-CVD process deposits SiO/sub 2/ films (PHOTOX /SUP TM/ ) at temperatures as low as 50/sup 0/C. The deposition process, the resulting film properties, and the use of PHOTOX SiO/sub 2/ for lateral isolation among transitors and vertical isolation between two-level interconnects are discussed. A novel process employing PHOTOX deposition in conjunction with a photoresist liftoff can be used to achieve totally isoplanar isolation. Photo-CVD can also be extended to produce other dielectrics such as silicon nitride and aluminum oxide.

Photo‐CVD for VLSI Isolation

This paper reviews the technique of photochemical‐assisted vapor deposition (photo‐CVD), and its applications in silicon IC processing. The photo‐CVD process deposits films (PHOTOX™) at temperatures as low as 50°C. The deposition process, the resulting film properties, and the use of PHOTOX for lateral isolation among transistors and vertical isolation between two‐level interconnects are discussed. A novel process employing PHOTOX deposition in conjunction with a photoresist liftoff can be used to achieve totally isoplanar isolation. Photo‐CVD can also be extended to produce other dielectrics such as silicon nitride and aluminum oxide.

Correlated Electrical and Microstructural Studies of Recrystallized Silicon Thin Films on Bulk Glass Substrates

ABSTRACTTo determine the nature and effect of defects which occur in the growth of crystalline semiconductor films on amorphous substrates, one must carry out microstructural and electrical studies on the same material regions. In previous publications we have demonstrated that by controlling optical absorption in and around delineated silicon areas, the nucleation and growth processes can be controlled. In this way we have been able to produce single crystal islands &gt;20 μm on a side. Using a simple, novel parylene lift –off technique we can now routinely study the material crystallized on bulk glass using transmission electron microscopy. We report here preliminary results of correlated electrical and structural studies on pre – patterned silicon films crystallized under various conditions. Electrical characterization consists mainly of I – V measurements on diodes and MOSFETS fabricated in the crystallized material by conventional silicon IC processing techniques. For microstructural characterization of the same devices we rely on TEM, EBIC and spatially– resolved Raman scattering.