Silicon Field Effect Transistors Research Articles

Piezo-VFETs: Vacuum Field Emission Transistors Controlled by Piezoelectric MEMS Sensors as an Artificial Mechanoreceptor with High Sensitivity and Low Power Consumption.

As one of the most promising electronic devices in the post-Moore era, nanoscale vacuum field emission transistors (VFETs) have garnered significant attention due to their unique electron transport mechanism featuring ballistic transport within vacuum channels. Existing research on these nanoscale vacuum channel devices has primarily focused on structural design for logic circuits. Studies exploring their application potential in other vital fields, such as sensors based on VFET, are more limited. In this study, for the first time, the design of a vacuum field emission transistor (VFET) coupled with a piezoelectric microelectromechanical (MEMS) sensing unit is proposed as the artificial mechanoreceptor for sensing purposes. With a negative threshold voltage similar to an N-channel depletion-mode metal oxide silicon field effect transistor, the proposed VFET has its continuous current tuned by the piezoelectric potential generated by the sensing unit, amplifying the magnitude of signals resulting from electromechanical coupling. Simulations have been conducted to validate the feasibility of such a configuration. As indictable from the simulation results, the proposed piezoelectric VFET exhibits high sensitivity and an electrically adjustable measurement range. Compared to the traditional combination of piezoelectric MEMS sensors and solid-state field effect transistors (FETs), the piezoelectric VFET design has a significantly reduced power consumption thanks to its continuous current that is orders of magnitude smaller. These findings reveal the immense potential of piezoelectric VFET in sensing applications, building up the basis for using VFETs for simple, effective, and low-power pre-amplification of piezoelectric MEMS sensors and broadening the application scope of VFET in general.

Features of Microwave Photoconductance of Quantum Point Contact and Silicon Field-Effect Transistor

Features of Microwave Photoconductance of Quantum Point Contact and Silicon Field-Effect Transistor

Measurement of cryoelectronics heating using a local quantum dot thermometer in silicon

Silicon technology offers the enticing opportunity for monolithic integration of quantum and classical electronic circuits. However, the power consumption levels of classical electronics may compromise the local chip temperature and hence the fidelity of qubit operations. Here, we utilize a quantum-dot-based thermometer embedded in an industry-standard silicon field-effect transistor (FET), to assess the local temperature increase produced by an active FET placed in close proximity. We study the impact of both static and dynamic operation regimes. When the FET is operated statically, we find a power budget of 45 nW at 100 nm separation whereas at 216 μm the power budget raises to 150 μW. When operated dynamically, we observe negligible temperature increase for the switch frequencies tested up to 10 MHz. Our work describes a method to accurately map out the available power budget at a distance from a solid-state quantum processor and indicate under which conditions cryoelectronics circuits may allow the operation of hybrid quantum-classical systems.

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

As silicon field-effect transistors encounter increasing scaling challenges, digital system designers are shifting their attention towards multi-valued logic (MVL), specifically ternary logic. The graphene nanoribbon field-effect transistor (GNRFET) emerges as a compelling alternative among post-MOSFET technologies for the implementation of ternary logic. This paper delves into the computational intricacies of ternary logic, underscores the outstanding features of GNRFET technology, and introduces a novel GNRFET-based 1-trit ternary multiplier (TMUL) requiring only 26 transistors. The performance of the design is assessed using the Synopsis HSPICE simulator with a 32-nm GNRFET model file operating at VDD = 0.9 V. The proposed TMUL surpasses existing designs due to its efficient paths with a minimal number of transistors for each output transition, a singular power supply voltage, and an extended voltage division scheme. In comparison to other contemporary TMUL designs, the proposed design exhibits a notable enhancement, showcasing a 21.42 % reduction in delay, a 33.11 % decrease in power-delay-product (PDP), and a 58.17 % decrease in energy-delay-product (EDP). Additionally, the design is subjected to thorough testing under diverse conditions including process, voltage, temperature (PVT) fluctuations, and load variations, validating its reliability and robustness.

Adiabatic Power Management Techniques for Metal Oxide Silicon Field Effect Transistors in Digital Logic Circuits

Metal Oxide Silicon Field Effect Transistors are foundational components in electronics, mainly digital logic circuits. Effective power management in MOSFET-based logic circuits becomes more crucial as technology expands to sub-100-nanometer nodes. Four optimization techniques to reduce power losses during switching transitions are carefully examined in this article. With the first method, QSSERL, no additional timing control clocks are required, which results in significant energy savings, especially in high-frequency applications. In the second method, DFAL, split-level sinusoidal power clocks are used instead of diodes, significantly lowering voltage differentials and power dissipation. Building on DFAL, IDFAL employs control transistors to reduce leakage power, significantly lowering power dissipation and facilitating charge recovery. Lastly, FSOA, inspired by natural species' collective behaviour, enhances key components within MOSFET-based circuits. This paper examines numerous adiabatic logic topics. Developing energy-efficient MOSFET-based logic circuits is essential for improving electronics and satisfying the growing demand for energy-conscious technologies.

Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular. Out of numerous ternary logic devices, carbon nanotube (CNT) FET (CNTFET) is considered a good candidate over silicon FETs. Hence, in this study, ternary schematics are developed based on Pseudo N-type CNTFETs. The ternary basic designs such as standard ternary inverter (STI), AND and OR gates are presented. Then, using the proposed basic logic gates, the complex designs such as full adder and full subtractor are also proposed. The HSPICE simulator is utilized to design proposed circuits and analyze different performance parameters. The performance such as delay, power and power delay product (PDP) are analyzed for the proposed circuits. Moreover, the proposed schematics performances are also compared to complementary schematics. It investigated that Pseudo N-type CNTFET schematics improved the overall performance on an average up to 65.82% over the complementary ternary circuits.

(Invited) BioFETs and Nanopore FETs: Nanoscale Silicon Field-Effect Transistors for Single-Molecule Sensing

High read throughput single-molecule sensing is a cornerstone of established third generation long-read DNA sequencing technologies and is crucial for emerging protein sequencing technologies. These omics technologies are of great interest for essential understanding and applications in the life sciences. Field Effect Transistor (FET)-based single-molecule sensors promise advances in omics, by further enhancing read throughput with massive parallelization.Here an overview is given of our recent progress on nanoscale bioFETs and nanopore FETs (NPFETs).A bioFET is a FET gated by a liquid electrolyte rather than by a solid gate. The FET is turned into a biosensor by attaching probe biomolecules to the gate dielectric. These probes bind specifically to the target biomolecule of interest. The attachment of the targets to the probes on the gate dielectric surface shifts the FET threshold voltage.A nanopore FET is an electrolytically gated FET as well, in which the gate gauges potential changes caused by a molecule moving, or translocating, through a nanopore, a nanoscale opening connecting two reservoirs. Nanopores have been firmly established as single-molecule sensors as the ionic current running through them is modulated by passing single molecules.Nanoscale silicon bioFET sensors have single-molecule capabilities within their reach [1-4]. To realize single-molecule sensing the single-molecule signal-to-noise ratio (SNR) must be sufficiently high. Downscaling the device area is key to increase SNR (∝1/√area) [5]. Although many reported FET sensors have nanoscale cross-sections, their gate lengths are typically micron-scale. Our FET modeling work shows that a sufficiently large single-molecule Signal-to-Noise Ratio (SNR) can be obtained when nano-scaling all FET channel dimensions [6]. We have shown significant progress [1] toward single-molecule detection by fabricating and characterizing finFET sensors with a gate length of 50nm and have shown that Si FETs have the potential to enable single-molecule sensing.Noise plays a central role in single-molecule sensing [7,8] and drift can also be a challenge in FET sensors [9]. Perhaps the greatest challenge for bioFETs is electrolyte screening which reduces the signal by masking the charge of target molecules with counterions. We have experimentally established the importance of non-linear screening, and the pH interference effect which can aggravate screening [10,11] and propose solutions.The nanopore FET, senses single molecules translocating through the pore due to the so-called resistive divider effect [6]. The nanopore FET has been experimentally demonstrated as a single-molecule sensor in 2012 [12]. The nanopore FET’s device-level advantage is its potential high > 100 MHz bandwidth with sufficient signal-to-noise ratio (SNR). This has been studied theoretically [13] but is yet to be proven experimentally. The second, and most important advantage, is the superior integrability of nanopore-FETs into large-scale arrays.In our recent simulation work making use of a dedicated nanofluidic nanodevice simulator we reveal that sensitivity can be boosted exponentially by increasing cis-trans bias [14].We have fabricated and characterized a Nanopore-FET milestone device [15,16], which has a nanopore running through a nanoscale silicon FET channel, but without bottom reservoir (see Fig. 1). On this milestone device we obtain excellent electrolytically gated FET transfer and output characteristics demonstrating a low subthreshold swing of 67mV/decade, indicating excellent device quality.Applications of the nanopore FET for omics and DNA data storage will be discussed.FET-based sensing promises to strongly enhance the read throughput of single-molecule sensing by means of massive parallelization.<ECSTEM.jpg>Fig. 1. TEM cross-section of the NPFET milestone device.[1] Santermans et al. IEEE International Electron Devices Meeting, 2020[2] Li et al. ACS Nano 2017, 11, 12789−12795[3] He et al. Angewandte Chemie, 55, 1, 2016[4] Li et al. Nanoscale, 2016, 8, 16172[5] Männik et al. Nano Letters, 8, 2008[6] Santermans et al., to be published[7] Martens et al. Int. Conf. Noise Fluctuations (ICNF), 2019[8] Bergfeld Mori et al. Solid-State Electronics 194, p. 108358, 2022[9] Wuytens et al. IEEE Int. Reliability Physics Symposium, 2020[10] Gupta, et al. IEEE Sensors Journal, 21, 4, p. 4143, 2020[11] Santermans et al. ACS Sensors 6, 3, p. 1049, 2021[12] Xie et al. Nature Nanotechnology, 7(2), pp.119-125, 2012[13] Parkin and Drndić, ACS sensors, 3, 2, p. 313, 2018[14] Verhulst et al., IEEE Sensors Journal, 22, 6, pp.5732-5742, 2022[15] Liu et al., MNE, Leuven, Sep., 2022[16] Martens et al. IEEE International Electron Devices Meeting, 2022 Figure 1

Identifying Pauli spin blockade using deep learning

Pauli spin blockade (PSB) can be employed as a great resource for spin qubit initialisation and readout even at elevated temperatures but it can be difficult to identify. We present a machine learning algorithm capable of automatically identifying PSB using charge transport measurements. The scarcity of PSB data is circumvented by training the algorithm with simulated data and by using cross-device validation. We demonstrate our approach on a silicon field-effect transistor device and report an accuracy of 96% on different test devices, giving evidence that the approach is robust to device variability. Our algorithm, an essential step for realising fully automatic qubit tuning, is expected to be employable across all types of quantum dot devices.

High-performance ternary designs using graphene nanoribbon transistors

Considering the issues emerging because of shrinking silicon field effect transistors (FETs), various post-silicon, post-binary logics are investigated by the researchers. The design of ternary schematics utilizing graphene nanoribbon FET (GNRFET) circuits is one alternate option. Since different threshold voltages are obtained by employing GNRFETs by varying its physical dimension, GNRFET is an ideal option for designing ternary circuits. The ternary circuit designs such as adder, subtractor and multiplier using GNRFETs are proposed in this study. These designs are developed using the ternary based decoder circuit. The proposed circuits are developed and executed in Synopsys based HSPICE simulator for functional verification. Additionally, the performances such as delay, power, power-delay-product (PDP) and energy-delay-product (EDP) of the proposed circuits are investigated and compared to CNTFET based ternary designs. The GNRFET ternary designs improved the performance on an average up to 30.96% than the CNTFET based designs.

Ballistic two-dimensional InSe transistors.

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm-1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V-1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.

Nanowire single-crystal grain and single grain boundary silicon field effect transistors for direct electrical characterization of grain boundaries

Single crystal grain (s-G) and single grain boundary (s-GB) Si field effect transistors (FETs) were investigated for direct measurement of the electrical activity of GBs. Ultrahigh-performance nanowire s-G FET with 1360 cm2V−1s−1 electron field-effect mobility (μ ef) was achieved on a transparent substrate. The significant difference of μ ef values between nanowire and microwire FETs proved that uniaxial tensile strain typically contributed to μ ef enhancement in nanowire FETs. Longitudinal GBs typically increased the leakage current and S factor due to a large donor concentration. The donor concentration generated by Σ3 and other CSL-type s-GBs was estimated.

A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm P SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS

This article presents a broadband sub-terahertz (THz) power amplifier (PA) with a low-loss four-way power combiner. The proposed power combiner consists of an improved zero-degree combiner (ZDC) and a three-conductor Marchand balun simultaneously achieving broadband matching and power combining. The proposed three-conductor Marchand balun adopts a dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank technique by merging two resonators, and it can be equivalent to a transformer-based multi-resonating network. The power distribution is realized by one input power splitter generating two pairs of differential signals and two parallel 1-to-2 active power splitters. This hybrid distribution driving network further enhances efficiency and power gain. Based on these improvements, a high-output-power sub-THz PA with superior efficiency has been fabricated in the 130-nm SiGe bipolar complementary metal oxide silicon field effect transistor (BiCMOS) technology. The three-stage PA achieves a peak power gain of 16.4 dB, 3-dB small-signal gain bandwidth of 52 GHz from 211 to 263 GHz, a measured maximum saturated output power of 14.7 dBm at 224 GHz, and a peak power-added efficiency (PAE) of 3.13% at 220 GHz. The folded input splitter and extremely compact power combining methodology lead to a core area of 770 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ </tex-math></inline-formula> .

Room-temperature several-hundred-of-megahertz charge sensing with single-electron resolution using a silicon transistor

We demonstrate charge detection with single-electron resolution at high readout frequency using a silicon field-effect transistor (FET) integrated with double resonant circuits. A FET, whose channel of 10-nm width enables a single electron to be detected at room temperature, is connected to resonant circuits composed of coupled inductors and capacitors, and these double resonant circuits provide two resonance frequencies. When the FET is driven by a carrier signal at the lower resonance frequency, a small signal applied to the FET's gate modulates the resonance condition, resulting in a reflected signal appearing near the higher resonance frequency. Such operation utilizing the double resonant circuits enables charge detection with a single-electron resolution of 3 × 10−3 e/Hz0.5 and a readout frequency of 200 MHz at room temperature. In addition, a variable capacitor used in the double resonant circuits allows charge-sensing characteristics to be controlled in situ.

Unraveling the impact of nano-scaling on silicon field-effect transistors for the detection of single-molecules.

Electrolyte-gated silicon field-effect transistors (FETs) capable of detecting single molecules could enable high-throughput molecular sensing chips to advance, for example, genomics or proteomics. For solid-gated silicon FETs it is well-known that nano-scaled devices become sensitive to single elementary charges near the silicon-oxide interface. However, in electrolyte-gated FETs, electrolyte screening strongly reduces sensitivity to charges near the gate oxide. The question arises whether nano-scaling electrolyte-gated FETs can entail a sufficiently large signal-to-noise ratio (SNR) for the detection of single molecules. We enhanced a technology computer-aided design tool with electrolyte screening models to calculate the impact of the FET geometry on the single-molecule signal and FET noise. Our continuum FET model shows that a sufficiently large single-molecule SNR is only obtained when nano-scaling all FET channel dimensions. Moreover, we show that the expected scaling trend of the single-molecule SNR breaks down and no longer results in improvements for geometries approaching the decananometer size. This is the characteristic size of the FET channel region modulated by a typical molecule. For gate lengths below 50 nm, the overlap of the modulated region with the highly conductive junctions leads to saturation of the SNR. For cross-sections below 10-30 nm, SNR degrades due to the overlap of the modulated region with the convex FET corners where a larger local gate capacitance reduces charge sensitivity. In our study, assuming a commercial solid-state FET noise amplitude, we find that a suspended nanowire FET architecture with 35 nm length and 5 × 10 nm2 cross-section results in the highest SNR of about 10 for a 15-base DNA oligo in a 15 mM electrolyte. In contrast with typical silicon nanowire FET sensors which possess micron-scale gate lengths, we find it to be key that all channel dimensions are scaled down to the decananometer range.

Tunable electrical contacts in two-dimensional silicon field-effect transistors: The significance of surface engineering

Two-dimensional silicon (2D-Si) semiconductor is highly desired for future field-effect transistors (FETs) due to the inherent compatibility with the silicon-based technology. Interfacial contact represents a significant bottleneck restricting the performance of 2D-Si-based FETs. Here, by first-principles calculations and quantum transport simulations, we propose a strategy of surface engineering by F-, H-, and OH-passivation to tune the electronic properties, electrical contacts, and device performance of 2D FETs based on monolayer dumbbell silicene (LHD-Si). It is found that surface passivation performed in the LHD-Si FETs can significantly eliminate the metal-induced gap states and greatly relieve the Fermi level pinning by improving the pinning factor from 0.08 to 0.46. Importantly, the LHD-Si monolayers passivated with F and OH prefer to form n-type and p-type contacts with the representative metals (Bi, Al, Ag, Cu, Au, and Pt), respectively. Among them, Ohmic or quasi-Ohmic contacts (with very small Schottky barrier) are realized for F-passivated (OH-passivated) LHD-Si with Bi/Al/Ag (Cu/Au/Pt) electrodes. In the particular case of LHD-Si FETs with Cu electrodes, n-type, p-type, and ambipolar-type transfer behaviors are obtained for the F-, OH–, and H-passivation, respectively, demonstrating the dominant role played by electrical contacts in determining the Schottky barrier of the devices. This work highlights the significance of surface engineering in tuning the electrical contact and transport properties of doping-free 2D-Si-based FETs.

Challenges and Opportunities for High-Power and High-Frequency AlGaN/GaN High-Electron-Mobility Transistor (HEMT) Applications: A Review.

The emergence of gallium nitride high-electron-mobility transistor (GaN HEMT) devices has the potential to deliver high power and high frequency with performances surpassing mainstream silicon and other advanced semiconductor field-effect transistor (FET) technologies. Nevertheless, HEMT devices suffer from certain parasitic and reliability concerns that limit their performance. This paper aims to review the latest experimental evidence regarding HEMT technologies on the parasitic issues that affect aluminum gallium nitride (AlGaN)/GaN HEMTs. The first part of this review provides a brief introduction to AlGaN/GaN HEMT technologies, and the second part outlines the challenges often faced during HEMT fabrication, such as normally-on operation, self-heating effects, current collapse, peak electric field distribution, gate leakages, and high ohmic contact resistance. Finally, a number of effective approaches to enhancing the device's performance are addressed.

Understanding and Controlling Band Alignment at the Metal/Germanium Interface for Future Electric Devices

Germanium (Ge) is a promising semiconductor as an alternative channel material to enhance performance in scaled silicon (Si) field-effect transistor (FET) devices. The gate stack of Ge FETs has been much improved based on extensive research thus far, demonstrating that the performance of Ge FETs is much superior to that of Si FETs in terms of the on-state current. However, to suppress the performance degradation due to parasitic contact resistance at the metal/Ge interface in advanced nodes, the reduction of the Schottky barrier height (SBH) at the metal/Ge interface is indispensable, yet the SBH at the common metal/Ge interface is difficult to control by the work function of metal due to strong Fermi level pinning (FLP) close to the valence band edge of Ge. However, the strong FLP could be alleviated by an ultrathin interface layer or a low free-electron-density metal, which makes it possible to lower the SBH for the conduction band edge of Ge to less than 0.3 eV. The FLP alleviation is reasonably understandable by weakening the intrinsic metal-induced gap states at the metal/Ge interface and might be a key solution for designing scaled Ge n-FETs.

An Aptamer-Functionalised Schottky-Field Effect Transistor for the Detection of Proteins.

The outbreak of the coronavirus disease 2019 (COVID-19) in December 2019 has highlighted the need for a flexible sensing system that can quickly and accurately determine the presence of biomarkers associated with the disease. This sensing system also needs to be easily adaptable to incorporate both novel diseases as well as changes in the existing ones. Here we report the feasibility of using a simple, low-cost silicon field-effect transistor functionalised with aptamers and designed to attach to the spike protein of SARS-CoV2. It is shown that a linear response can be obtained in a concentration range of 100 fM to 10 pM. Furthermore, by using a larger range of source-drain potentials compared with other FET based sensors, it is possible to look at a wider range of device parameters to optimise the response.

Trench field-effect transistors integrated in a microfluidic channel and design considerations for charge detection.

Field-effect transistors (FETs) combined with a microfluidic system allow for the electrical detection of charged materials moving in a microfluidic channel. Here, we demonstrate trench-shaped silicon FETs with the combination of a microfluidic channel that can be used for simultaneous electrical and optical detection of charged fluorescent beads. The n-channel silicon trench FETs have a maximum transconductance of 1.83 × 10-5 S at near-zero gate bias voltage, which is beneficial for the high sensitivity of electrical detection. The optical transparency and physical robustness of the integrated microfluidic channel are achieved by a polydimethylsiloxane (PDMS)/glass hybrid cover combining the good sealing characteristics of PDMS, and the thin and flat properties of glass. Device evaluation methodologies and measurement approaches are also presented demonstrating a synchronized time-lapse imaging and electronic detection of bead transport. The proposed device and design consideration could advance the promise of electronic sensing to measure potential differences induced by charged analytes.

Tunable Electrical Contacts in Two-Dimensional Silicon Field-Effect Transistors: The Significance of Surface Engineering

Tunable Electrical Contacts in Two-Dimensional Silicon Field-Effect Transistors: The Significance of Surface Engineering