Fabrication Of Silicon Research Articles

Nanoscale Silicon Fingerprints for Counterfeit Prevention in Microchips.

The increasing vulnerability of microchips to counterfeiting poses a significant threat to nations, companies, and the general public. Creating a unique "fingerprint" on each chip using intrinsic manufacturing variations can significantly prevent the number of fraudulent chips. Since Si-based semiconductor fabrication processes are now flawless down to a few nanometers, finding a high-entropy source at the nanoscale has become challenging. Inspired by the concept of physical unclonable function, this work reports the CMOS-compatible and lithography-free fabrication of unique nanostructured silicon "fingerprints." Nanostructuring is achieved via low-temperature dewetting and metal-assisted chemical etching, which produces a high level of entropy and unique silicon-based nanoscale fingerprints with linewidths tunable from ≈8 to 140nm, commensurate with the dimensions of mainstream microfabrication processes. These Si nanofingerprints are highly reliable for chip authentication and against reverse engineering, providing a large encoding capacity of up to 216384/µm2. For practical applications, detection of fingerprints protected with a polymer coating is demonstrated using back-scattered electron imaging.

Structural and optical properties of black silicon prepared by wet chemical etching

The study focuses on the optimization of black silicon fabrication via etching using a solution composed of KOH, NaOH, and Na2SiO3 at constant concentrations and varying durations. Surface morphology was analyzed using Field Emission Scanning Electron Microscopy (FE-SEM). The results showed that pyramidal structures were formed on the silicon surface with heights between 1.2 and 4.1 μm. The uniform distribution was confirmed by AFM images. The surface roughness decreased as the etching time increased; it was measured at 14.03 nm for 15 minutes and 5.59 nm for 30 minutes. The properties of photoluminescence (PL) were evaluated using a spectrometer and it was found that peak emission shifts to lower energies (red shift) when etching time is increased. Optical reflectivity decreases sharply when etching time is increased. Additionally, the longer the etching duration, the greater the energy gap of the material which increased from 1.25 eV to approximately 1.4 eV.

Fabrication of Microcrystalline Silicon Thin Film by Ionized Physical Vapor Deposition Process

The present manuscript describes the fabrication of microcrystalline silicon (µc-Si) thin films at room temperature using the ionized physical vapor deposition (iPVD) process. The iPVD chamber incorporates a planar DC magnetron and an additional RF coil to generate an intermediate dense plasma region between the target and the substrate. The intermediate dense plasma enhances the ionization of sputtered neutral Si atoms before deposition in the iPVD process. This process greatly impacts the structural, morphological, and optical characteristics of the Si thin films. X-ray diffraction (XRD) reveals that conventional PVD produces an amorphous Si thin film, while iPVD yields a µc-Si thin film with peaks at 28.5° and 47.3°, corresponding to the (111) and (220) planes of Si. Raman spectroscopy confirms the microcrystalline nature of the Si thin film, showing approximately 70% crystallinity in the iPVD process. FESEM images display a granular structure for PVD and a cauliflower-like structure for the iPVD process. AFM images indicate a significant reduction in surface roughness for iPVD films compared to the PVD process. UV-Visible absorption spectroscopy shows that the optical band gap (Eg) decreases from (1.7 ± 0.08) eV to (1.4 ± 0.05) eV while shifting from the PVD to iPVD process.

Lithium niobate electro-optical modulator based on ion-cut wafer scale heterogeneous bonding on patterned SOI wafers

This paper presents the design, fabrication, and characterization of a high-performance heterogeneous silicon on insulator (SOI)/thin film lithium niobate (TFLN) electro-optical modulator based on wafer-scale direct bonding followed by ion-cut technology. The SOI wafer has been processed by an 8 inch standard fabrication line and cut into 6 inch for direct bonding with TFLN. The hybrid SOI/LN electro-optical modulator operated at the wavelength of 1.55 μm is composed of couplers on the Si layer and a Mach–Zehnder interferometer (MZI) structure on the LN layer. The fabricated device exhibits a stable value of the product of half-wave voltage and length (V π L) of around 2.9 V·cm. It shows a good low-frequency electro-optic response flatness and supports 96 Gbit/s data transmission for the NRZ format and 192 Gbit/s data transmission for the PAM-4 format.

Fabricating 3D Si nanostructure via a novel Ga+ implantation enabled maskless dry etching process

Three-dimensional (3D) nanostructure is the key to the miniaturization of nonlinear photonic and electronic devices. Because of the great demand on the ultra-small nanostructures, the novel nanofabrication technologies with flexible 3D silicon (Si) fabrication capability are of great importance. Herein, by combining Ga+ FIB implantation and ICP dry etching processes, we proposed a novel Ga+ FIB implantation assisted maskless dry etching technology for direct fabrication of 3D Si nanostructures. We found that the implanted Ga+ induced amorphization layer in Si substrate acts as the ‘quasi-mask’ during the ICP dry etching process. The increase of Ga+ concentration in amorphization layer of Si substrate improves the etching resistance of the area. Moreover, enabled by high resolution and flexibility of FIB, the proposed technology is capable of directly fabricating various 3D Si nanostructures in a simple way, such as 3D nanoscale artificial bowtie arrays with sub-10 nm gaps, multi-scale 3D Si nanostructures with arbitrary patterns. More importantly, the proposed technology is compatible to current semiconductor manufacturing process. Benefiting by the advantages of simplicity and high efficiency, the proposed maskless dry etching process promises great application potential in the fields of nonlinear photonics and micro-electronics.

Diameter controlled fabrication of ultralong silicon wires through regulating metal mass in massive metal-assisted chemical vapor deposition

Abstract The successful fabrication of ultra-long silicon wires has facilitated the study and application of silicon wires. However, research on the controlled fabrication of ultralong silicon wires, such as diameter modulation, is still insufficient. Herein, tapering ultralong silicon wires are synthesized by using a massive metal-assisted chemical vapor deposition method. By altering the mass of the tin catalyst in the growth zone, the length and changing rate of the diameter can be modulated. When a 40 g catalyst is placed in the growth region, the length of obtained silicon wires is 6.6 mm, and the changing rate of diameter with length is 541 nm/mm. When the catalyst mass in the growth region is reduced to 20 g, the length of the products decreases to 4.0 mm, and the changing rate of diameter with length increases to 964 nm/mm. This work proposes a new route for the diameter-modulated fabrication of ultralong silicon wires and will promote their application across various fields.

Fabrication of nitrogen-hyperdoped silicon by high-pressure gas immersion excimer laser doping

In recent years, research on hyperdoped semiconductors has accelerated, displaying dopant concentrations far exceeding solubility limits to surpass the limitations of conventionally doped materials. Nitrogen defects in silicon have been extensively investigated for their unique characteristics compared to other pnictogen dopants. However, previous practical investigations have encountered challenges in achieving high nitrogen defect concentrations due to the low solubility and diffusivity of nitrogen in silicon, and the necessary non-equilibrium techniques, such as ion implantation, resulting in crystal damage and amorphisation. In this study, we present a single-step technique called high-pressure gas immersion excimer laser doping (HP-GIELD) to manufacture nitrogen-hyperdoped silicon. Our approach offers ultrafast processing, scalability, high control, and reproducibility. Employing HP-GIELD, we achieved nitrogen concentrations exceeding 6 at% (3.01 × 1021 at/cm3) in intrinsic silicon. Notably, nitrogen concentration remained above the liquid solubility limit to ~1 µm in depth. HP-GIELD’s high-pressure environment effectively suppressed physical surface damage and the generation of silicon dangling bonds, while the well-known effects of pulsed laser annealing (PLA) preserved crystallinity. Additionally, we conducted a theoretical analysis of light-matter interactions and thermal effects governing nitrogen diffusion during HP-GIELD, which provided insights into the doping mechanism. Leveraging excimer lasers, our method is well-suited for integration into high-volume semiconductor manufacturing, particularly front-end-of-line processes.

A basic introduction to integrated circuit technology

This paper summarizes and synthesizes the research findings of previous scholars, starting from the fabrication of single-crystal silicon to wafer processing and the final chip manufacturing. Additionally, it analyzes the domestic and international integrated circuit industry chains and markets, elucidating the levels and characteristics of the technology both domestically and internationally. This paper aims to provide readers with a comprehensive understanding of the various processes and steps involved in the production of integrated circuits, and to enable readers to develop a preliminary and fundamental understanding of the integrated circuit industry.

Wafer-scale fabrication of mesoporous silicon functionalized with electrically conductive polymers

The fabrication of hybrid materials consisting of nanoporous hosts with conductive polymers is a challenging task, since the extreme spatial confinement often conflicts with the stringent physico-chemical requirements for polymerization of organic constituents. Here, several low-threshold and scalable synthesis routes for such hybrids are presented. First, the electrochemical synthesis of composites based on mesoporous silicon (pSi) and the polymers PANI, PPy and PEDOT is discussed and validated by scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDX). Polymer filling degrees of ≥74 % are achieved. Second, the production of PEDOT/pSi hybrids, based on the solid-state polymerization (SSP) of DBEDOT to PEDOT is shown. The resulting amorphous structure of the nanopore-embedded PEDOT is investigated via in-situ synchrotron-based X-ray scattering. In addition, a twofold increase in the electrical conductivity of the hybrid compared to the porous silicon host is shown, making this system particularly promising for thermoelectric applications.

An experimental investigation of spin-on doping optimization for enhanced electrical characteristics in silicon homojunction solar cells: Proof of concept

The pursuit of enhancing the performance of silicon-based solar cells is pivotal for the progression of solar photovoltaics as the most potential renewable energy technologies. Despite the existence of sophisticated methods like diffusion and ion implantation for doping phosphorus into p-type silicon wafers in the semiconductor industry, there is a compelling need to research spin-on doping techniques, especially in the context of tandem devices, where fabricating the bottom cell demands meticulous control over conditions. The primary challenge with existing silicon cell fabrication methods lies in their complexity, cost, and environmental concerns. Thus, this research focuses on the optimization of parameters, such as, deposition of the spin on doping layer, emitter thickness (Xj), and dopant concentration (ND) to maximize solar cell efficiency. We utilized both fabrication and simulation techniques to delve into these factors. Employing silicon wafer thickness of 625 μm, the study explored the effects of altering the count of dopant layers through the spin-on dopant (SOD) technique in the device fabrication. Interestingly, the increase of the dopant layers from 1 to 4 enhances efficiency, whereby, further addition of 6 and 8 layers worsens both series and shunt resistances, affecting the solar cell performance. The peak efficiency of 11.75 % achieved in fabrication of 4 layers dopant. By using device simulation with wxAMPS to perform a combinatorial analysis of Xj and ND, we further identified the optimal conditions for an emitter to achieve peak performance. Altering Xj between 0.05 μm and 10 μm and adjusting ND from 1e+15 cm−3 to 9e+15 cm−3, we found that maximum efficiency of 14.18 % was attained for Xj = 1 μm and ND = 9e+15 cm−3. This research addresses a crucial knowledge gap, providing insights for creating more efficient, cost-effective, and flexible silicon solar cells, thereby enhancing their viability as a sustainable energy source.

Lithography‐Free Method to Synthesize Quasiperiodic Silicon Inverted‐Pyramid Arrays: A Broadband Light Trapper for High‐Efficiency Thin Silicon Solar Cells

Thin silicon solar cells can be a low‐cost effective photo‐conversion device, if the device can efficiently absorb the solar spectrum. Herein, a new lithography‐free technique is developed for the fabrication of quasiperiodic silicon inverted‐pyramids arrays (SiIPAs), which show a high‐light‐trapping phenomenon in the ultraviolet–visible—near‐infrared (300–2000 nm). Fabricated SiIPA samples show a significant reduction of reflectance (3%) in the silicon absorption band (300–1000 nm). A unique additional absorption of 33–44% compared to the planar silicon is observed in the sub‐bandgap region of silicon (1100–2000 nm) for these samples. Photocurrent response measurement confirms the generation of additional electron–hole pairs in the sub‐bandgap region of silicon for the SiIPA samples in comparison with planar sample. In these results, the effect of field confinement and the creation of optical resonance modes within these structures, qualitatively supported by numerical simulation, are signified. The estimated short‐circuit current density using the experimental absorption spectrum of SiIPAs is 55.46 mA cm−2, which is far higher than the Lambertian limit of ≈43 mA cm−2. The theoretical efficiency of the solar cell can be achieved up to 35.22%, which surpasses the Shockley–Queisser limit of 33.7%.

Low-temperature fabrication of boron-doped amorphous silicon passivating contact as a local selective emitter for high-efficiency n-type TOPCon solar cells

Tunnel oxide passivating contact (TOPCon) solar cells (SCs) currently dominate the photovoltaic industry but grapple with efficiency challenges. A primary concern is the direct contact between front-sided metal electrodes and boron emitters, resulting in substantial carrier recombination losses and limiting further efficiency improvements. Here, we introduce a low-temperature approach to deposit a local boron-doped amorphous silicon [a-Si:H(p)] between front-sided metal electrodes and boron emitters. This method, avoiding issues associated with high-temperature processes, demonstrates excellent passivation and contact properties, featuring the lowest contact resistivity (< 1 mΩ·cm2) and a low saturation current density (< 400 fA/cm2). The outstanding passivation and contact properties remain robust even with variations in diborane flow rates during a-Si:H(p) fabrication, annealing temperatures, and sheet resistances of boron emitters. We elucidate the factors contributing to the enhanced passivation observed in boron emitters with a-Si:H(p) through a combination of simulations and experiments. The a-Si:H(p) layer between boron emitters and metal electrodes acts as a protective barrier, preventing the diffusion of metal atoms and suppressing carrier recombination. A heterojunction is formed between a-Si:H(p) and the boron emitter, facilitating electric-field passivation. Consequently, the TOPCon SCs incorporating a-Si:H(p) achieve an efficiency of 24.50%, surpassing their counterparts without a-Si:H(p) (23.11%). This work utilizes low-temperature technology to achieve fully passivated contact, providing insights for the development of high-efficiency TOPCon SCs.

Fabrication of silicone foam/polytitanosiloxane composite with enhanced flame retardancy

In this research, a series of silicone foam/polytitanosiloxane composites (SF-pTS) were fabricated with hydroxy-, vinyl-, hydrogen-containing polydimethylsiloxanes, and polytitanosiloxane filler in the presence of a platinum catalyst under ambient conditions. The effect of the amount of polytitasiloxane on the micromorphology and flame retardancy of silicone foam was studied, and a relative flame retardancy mechanism was proposed. It could be found that the polytitanosiloxane exhibited a good dispersion level in the silicone foam, thus improving the flame retardancy of the composite. When the content of polytitanosiloxane is 9 wt%, the limiting oxygen index and UL-94 grade of the SF-pTS9 composite are increased to 29.2% and FV-0, respectively. Cone experiment results suggested that the SF-pTS9 possessed relative balanced PHRR (148.9 kW/m2), THR (58.5 MJ/m2), TSP (0.6 m2), and mass residue (83.9%) among the prepared silicone foam materials. This work provides a new avenue to fabricate a silicone foam composite with enhanced flame retardancy.

Solution-processed nickel oxide passivation on large-area silicon electrodes for efficient photoelectrochemical water splitting

In this research, we report the large-scale fabrication of nickel oxide-coated n-type silicon (n-Si) photoanodes via chemical bath deposition for efficient photoelectrochemical water oxidation.

(Invited) Direct Ink Writing of Supercapacitors for Flexible and Wearable Applications

Direct Ink Writing (DIW) has recently emerged as a revolutionizing 3D printing technology for automated, cost-effective, and smart manufacturing of flexible and wearable electronic devices. Due to huge potential of flexible and wearable electronic devices in healthcare, sports, portable electronics, aircraft structures, robotics, etc., it is imperative to find the reliable and cost-effective methods to shift conventional rigid electronics to flexible/ wearable electronics. DIW process is highly efficient to fabricate high performance supercapacitors due to its processing capability to print wide range of materials and its simplicity. This work is focused on the fabrication of silicon and graphene-based supercapacitors using DIW and their application for flexible, stretchable, and wearable electronics. Different critical parameters for DIW such as rheology requirements of inks, material selection for electrode/ electrolyte, surface requirements to ensure better adhesion between printing layers, mechanical/ material testing of fabricated devices, and their electrochemical performance have been discussed to get a reliable energy storage device.

Role of Metal Nanoparticles in the Fabrication of Porous Silicon: A Material for Solar Cell Applications

Metal-Assisted Chemical Etching method (MACE) has emerged as an effective tool to fabricate silicon nanostructures. This technique requires a catalytic mask that is commonly composed of a metal. In the present work, the role of Silver nanoparticles (AgNPs) in the etching mechanism of Porous Silicon (PS) is investigated by studying the effect of AgNP coverage on the surface porosity and the different properties of PS. XRD spectra consist of the two peaks corresponding to silicon and AgNPs respectively and the peak intensity of Ag decreased with an increase in etching time which indicates that as the etching time increases the dissolution of silver metal also increases. Thus, the pore depth depends on the dissolution of AgNP. The pore depth and porosity are calculated at different etching times by SEM analysis. It is observed that porosity is modifiable with the variation of AgNP coverage which in turn modifies the optical properties of PS. The porosity increased with the increase of etching time and the highest porosity obtained was 78% after 240 minutes. The refractive index of PS decreased with increasing porosity in the visible region. The variation of the refractive index results in the tuning of optical energy gap which is more essential in increasing the efficiency of solar cells.

Fabrication and Characterization Study of Porous Silicon for NIR-VIS Photodetector Applications

In this paper, photoelectrochemical etching of the n-type silicon (n-Si) wafers is used to prepare porous silicon (PSi) with current density of 10 mA.cm[Formula: see text] for 10 min. Moreover, the structural and morphological properties of the n-PSi were analyzed by using XRD and AFM, FTIR and PL. XRD patterns of PSi show that the films are single-crystalline, with cubic structure. The major peak characteristics are allocated to plane (004). The atomic force microscope image and the distribution chart of the grains of the n-PSi displayed that the grain sizes were −8.98. FTIR is a powerful and easy-to-use technique to obtain the surface chemical state of PSi. The convenience results from the transparency of silicon for IR light and the high surface area. The basic features begin from the knowledge of the bondings to hydrogen, [Si–H], and to oxygen [Si–O]. The model calculations sometimes provide useful information in the assignment. By examining FTIR, the active bonds showed the formation of PSi. PL spectra were measured in the range of (600–900) nm, the emission peak for the fixed excitation wavelength at 500 nm, and spectral 1.78 eV and 1.24 eV. PSi is recognized as an attractive building block for photonic devices because of its novel properties including high ratio of surface to volume and high light absorption. We first report NIR and VIS (PDs) fabricated by PSi as a carrier collector and a photoexcitation layer.

Single-Step Fabrication of Resonant Silicon–Gold Hybrid Nanoparticles for Efficient Optical Heating and Nanothermometry in Cells

Single-Step Fabrication of Resonant Silicon–Gold Hybrid Nanoparticles for Efficient Optical Heating and Nanothermometry in Cells

All silicon MIR super absorber using fractal metasurfaces

Perfect absorbers can be used in photodetectors, thermal imaging, microbolometers, and thermal photovoltaic solar energy conversions. The spectrum of Mid-infrared (MIR) wavelengths offers numerous advantages across a wide range of applications. In this work, we propose a fractal MIR broadband absorber which is composed of three layers: metal, dielectric, and metal (MDM), with the metal being considered as n-type doped silicon (D-Si) and the dielectric is silicon carbide (SiC). The architectural design was derived from the Sierpinski carpet fractal, and different building blocks were simulated to attain optimal absorption. The 3D finite element method (FEM) approach using COMSOL Multiphysics software is used to obtain numerical results. The suggested fractal absorber exhibits high absorption enhancement for MIR in the range between 3 and 9 µm. D-Si exhibits superior performance compared to metals in energy harvesting applications that utilize plasmonics at the mid-infrared range. Typically, semiconductors exhibit rougher surfaces than noble metals, resulting in lower scattering losses. Moreover, silicon presents various advantages, including compatibility with complementary metal–oxide–semiconductor (CMOS) and simple manufacturing through conventional silicon fabrication methods. In addition, the utilization of doped silicon material in the mid-IR region facilitates the development of microscale integrated plasmonic devices.

Novel process integration flow of germanium-on-silicon FinFETs for low-power technologies

Germanium channel FinFET transistors process integration on a silicon substrate is a promising candidate to extend the complementary metal–oxide–semiconductor semiconductor roadmap. This process has utilized the legacy of state-of-art silicon fabrication process technology and can be an immediate solution to integrate beyond Si channel materials over standard Si wafers. The fabrication of such devices involves several complicated technological steps, such as strain-free epi layers over the Si substrate to limit the substrate leakage and patterning of narrow and sharp fins over germanium (Ge). To overcome these issues, the active p-type germanium layers were grown over n-type germanium and virtual substrates. The poly ((4-(methacryloyloxy) phenyl) dimethyl sulfoniumtriflate) was utilized as a polymeric negative tone e-beam resist for sub-20 nm critical dimensions with low line edge roughness, line width roughness, and high etch resistance to pattern p-Ge fins to meet these concerns. Here, the devices use the mesa architecture that will allow low bandgap materials only at the active regions and raised fins to reduce the active area interaction with the substrate to suppress leakage currents. This paper discusses the simple five-layer process flow to fabricate FinFET devices with critical optimizations like resist prerequisite optimization conditions before exposure, alignment of various layers by electron beam alignment, pattern transfer optimizations using reactive ion etching, and bilayer resist for desired lift-off. The Ge-on-Si FinFET devices are fabricated with a width and gate length of 15/90 nm, respectively. The devices exhibit the improved ION/IOFF in order of ∼105, transconductance Gm ∼86 μS/μm, and subthreshold slope close to ∼90 mV/dec.