Silicon-controlled Rectifier Device Research Articles

ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process

To effectively protect the radio-frequency (RF) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, the silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD protection devices due to their high ESD robustness and low parasitic capacitance. In this paper, an SCR device assisted with an inductor is proposed to improve the turn-on efficiency for ESD protection. Besides, the inductor can be also designed to resonate with the parasitic capacitance of the SCR device at the selected frequency band for RF performance fine tuning. Experimental results of the ESD protection design with inductor-triggered SCR in a nanoscale CMOS process have been successfully verified at 60-GHz frequency. The ESD protection design with inductor-triggered SCR has been implemented in cell configuration with compact size, which can be directly used in the RF receiver circuits. To verify the RF characteristics and ESD robustness in the RF receiver, the inductor-triggered SCR has been applied to a 60-GHz low-noise amplifier (LNA). Verified in a silicon chip, the 60-GHz LNA with the inductor-triggered SCR can achieve good RF performances and high ESD robustness.

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.

Low-Capacitance SCR With Waffle Layout Structure for On-Chip ESD Protection in RF ICs

The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (ICs). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.

Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products.

SCR Device Fabricated With Dummy-Gate Structure to Improve Turn-On Speed for Effective ESD Protection in CMOS Technology

Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-/spl mu/m CMOS process with a gate-oxide thickness of /spl sim/50 /spl Aring/, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.

A Novel Gate-Coupled SCR ESD Protection Structure With High Latchup Immunity for High-Speed I/O Pad

A novel electrostatic discharge (ESD) protection device, namely, a highly latchup-immune gate-coupled p-type low-voltage-trigger silicon-controlled rectifier, has been demonstrated to be an effective ESD protection device with low capacitive-loading effect. With the proper control circuit, a trigger voltage higher than 10 V and a trigger current larger than 90 mA can be achieved, while the holding voltage is still higher than 3 V under normal operation, which provides excellent latchup immunity. In the event of an ESD, this novel silicon-controlled rectifier device could trigger quickly and provide an effective discharging path.

SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as an on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in sub-quarter-micron CMOS processes. From the experimental results, the switching voltage and turn-on time of such double-triggered SCR (DT-SCR) device has been confirmed to be significantly reduced by this double-triggered technique.

Latchup-free esd protection design with complementary substrate-triggered scr devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process

The turn-on mechanism of a silicon-controlled rectifier (SCR) device is essentially a current triggering event. While a current is applied to the base or substrate of the SCR device, it can be quickly triggered into its latching state. In this paper, a novel design concept to turn on the SCR device by applying the substrate-triggered technique is first proposed for effective on-chip electrostatic discharge (ESD) protection. This novel substrate-triggered SCR device has the advantages of controllable switching voltage and adjustable holding voltage and is compatible with general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. Moreover, the substrate-triggered SCR devices can be stacked in ESD protection circuits to avoid the transient-induced latch-up issue. The turn-on time of the proposed substrate-triggered SCR devices can be reduced from 27.4 to 7.8 ns by the substrate-triggering technique. The substrate-triggered SCR device with a small active area of only 20 /spl mu/m /spl times/ 20 /spl mu/m can sustain the HBM ESD stress of 6.5 kV in a fully silicided 0.25-/spl mu/m CMOS process.

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.

Complementary two-transistor circuits and negative differential resistance

The DC behavior of nonlinear one-ports using two complementary Ebers-Moll-modeled transistors and lacking internal independent sources is discussed. It is proven that, in the absence of internal resistors, all such one-ports-irrespective of their internal topology and transistor parameter values-cannot exhibit negative differential resistance (NDR) for any value of an external biasing current source. One circuit using two complementary transistors and no resistors is of particular interest, since it is often cited as a two-transistor simplified model for silicon-controlled rectifier devices. The results demonstrate that either the transistor behavior unaccounted for in an Ebers-Moll-type model must be involved in this one-port's NDR behavior, or the presence of internal resistors is essential to such a circuit's behavior having even a generally correct qualitative character. >