Silicon-controlled Rectifier Device Research Articles

A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions.

Design of a LVTSCR triggered SCR device for low voltage ESD protection

In this paper, a novel silicon-controlled rectifier (SCR) electrostatic discharge (ESD) protection device, called low voltage triggered SCR (LVTSCR) triggered SCR (LVTSCRTSCR), is proposed for 3.3 V I/O protection applications in 0.18 μm CMOS technology. One side of the device is the traditional LVTSCR structure, and other side is the traditional SCR structure. The two structures are connected by a floating P+ diffusion layer. The working principle of LVTSCRTSCR was verified by the TCAD simulation results and TLP test results. The test results show that the triggering voltage of LVTSCRTSCR is determined by the traditional LVTSCR, with a value of 9.850 V. The holding voltage of the device can be effectively improved by increasing the size of the floating diffusion layer D4. When D4 = 6 μm, the holding voltage can be 4.491 V, suitable for 3.3 V I/O.

Principle and verification of behavior model of gate-controlled SCR with adjustable on-resistance

This paper delineates the implementation of a gate-controlled Silicon Controlled Rectifier (SCR) behavioral model using Cadence software. The model is designed to tackle the absence of gate-control effect characteristics in extant models. This enables more precise simulation of the snapback behavior of such gate-controlled SCR devices under electrostatic discharge (ESD) stress. This work fabricates three types of SCR devices: Traditional SCR(T-SCR), Single-Gate SCR (SG-SCR), and a Double-Gate SCR (DG-SCR). These devices are fabricated using the 0.18 μm CMOS process and varied in the number of gates. The physical principles of the device are validated through two-dimensional electrical simulations. Furthermore, the model results are confirmed by the transmission line pulse (TLP) test results of the final device. The results demonstrate that the simulation results of the gate-controlled SCR behavioral model fit the TLP test results of the three SCR devices. The model’s applicability across different number of fingers devices confirms its scalability. Further, the model was simulated with the HBM equivalent circuit, and the comparison with the actual results confirmed the model’s applicability to HBM simulation.

Investigation on holding voltage of asymmetric DDSCR with floating heavy doping in 0.18 μm CMOS process

In the ESD protection design work, the most effective way to improve the holding voltage of bidirectional silicon-controlled rectifier or SCR device is to increase the distance between the cathode and anode of it. However, for DDSCR devices with multi-finger layouts, increasing this distance will result in a decrease in failure current and require a larger layout area. In this work, five types of asymmetric dual direction silicon-controlled rectifier devices with different floating heavy doping combinations are designed based on the traditional ADDSCR structure. Meanwhile, the dimensions, number of fingers, metal layout and number of CONT holes of the five ADDSCR structures are strictly kept the same, aiming at studying the influence of different floating heavy doping combinations on the performance of SCR devices and find the optimal floating heavy doping combination. Their ESD performances are predicted and verified through the two-dimensional device simulations and transmission line pulse (TLP) test results. All the five types of ADDSCR structures are designed to improve the holding voltage. From the results, the forward and reverse holding voltage of ADDSCR_PP, which is inserted floating P+ in NW and PW, are increased to 20.4 V and 17.6 V respectively, compared with the traditional devices without floating heavy doping at 14.2 V and 8.7 V. At the same time, the physical mechanism for the effect of floating heavy doping insert into NW and PW separately were investigated. Finally, the one that best meets the ESD window of automotive application is found.

Study on the high-temperature triggering and holding characteristics of PDSOI SCR devices

In this paper, the triggering and holding characteristics of electrostatic discharge (ESD) protection devices operating under various ambient temperatures ranging from 25 °C to 300 °C are investigated. The measured ESD protection devices were silicon-controlled rectifier (SCR) devices fabricated in 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. Measurements were conducted using the transmission line pulse (TLP) test system. The triggering voltage, VT1, and the holding voltage, VH, of the SCR devices show negative coefficient phenomenon with the increasing temperature. The similarities and differences between the triggering condition and the holding condition are analyzed in detail. The underlying physical mechanisms related to the effects of temperature on the VT1 and VH are provided by the assist of technology computer-aided design (TCAD) simulation.

Schottky-Embedded Silicon-Controlled Rectifier With High Holding Voltage Realized in a 0.18-μm Low-Voltage CMOS Process

The silicon-controlled rectifier (SCR) has been reported to protect CMOS integrated circuits (ICs), due to high ESD robustness within a small silicon area. However, the holding voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> ) of the SCR device was too low to suffer the latch-up issue. Thus, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> value of the SCR device must be improved to be greater than the circuit operating voltage for safe applications. In this work, the Schottky-embedded modified lateral SCR (SMLSCR) with high holding voltage for ESD protection was proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. By using the Schottky barrier junction, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> value of the SCR device can be improved by the reverse-bias Schottky barrier diode (SBD) that is embedded into the SCR device structure. Among those experimental results on the SMLSCR devices with split layout parameters in the silicon test chip, the SMLSCR device without P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> guard ring has the best second breakdown current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t2</sub> ) of 3.1 A and a high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> value of 9.7 V.

A High Failure-Current Gate-Controlled Dual-Direction SCR for High-Voltage ESD Protection in 0.18-μm BCD Technology

To make a dual-direction silicon-controlled rectifier (SCR) that is highly robust in a high-voltage environment, a gate-controlled dual-direction SCR (GC-DDSCR) device is proposed. After analyzing the working principle of the device through the equivalent circuit and 2-D device simulation, the electro-static discharge (ESD) characteristics of the device are verified through the transmission line pulse (TLP) test. The failure current of the GC-DDSCR structure is greatly improved to 14.19 A compared with only 3.53 A of the same size traditional dual-direction SCR (TDDSCR) structure. The trigger voltage and the holding voltage of the GC-DDSCR are 24.23 and 20.15 V, respectively. In addition, this article explains the principle of GC-DDSCR devices with high protection capability. That is, because the device has a polysilicon gate electrode shorted to the anode (cathode), the electric field effect generated by the gate promotes carrier movement in the SCR path. Thus, the electric field force promotes the opening of the SCR path of the device and the direction of the electric field force is always consistent with the current direction. The overall failure capability of the device is effectively improved.

$\pi$ -SCR Device for Broadband ESD Protection in Low-Voltage CMOS Technology

Electrostatic discharge (ESD) protection design is needed for integrated circuits; however, the ESD protection devices near the I/O pad may cause negative impacts on the high-frequency performance. To achieve both excellent ESD robustness and good broadband performance, a silicon-controlled rectifier (SCR) with trigger diodes, a matching inductor, and a reversed diode to form a novel $\pi $ -SCR device is presented in this brief. As compared with the conventional $\pi $ -diode in silicon, the $\pi $ -SCR can reduce the clamping voltage during the critical positive-to- $V_{\text {SS}}$ (PS) ESD test, and the high-frequency performance is not seriously degraded (insertion loss $\pi $ -SCR device does not suffer the latch-up issue in low-voltage CMOS technology, and it has the potential to further reduce the clamping voltage during other ESD tests. Therefore, the novel $\pi $ -SCR device will be a good choice for broadband ESD protection in low-voltage CMOS technology.

A compact LDMOS DDSCR for HV ESD protections with high robustness and reliability

The LDMOS-based silicon controlled rectifier (SCR) is commonly used in high voltage (HV) electrostatic discharge (ESD) protection due to its great current handling capability per area and HV protection ability. In this paper, an improved LDMOS-based dual direction SCR (LDMOS-DDSCR) device is designed by replacing floating N+ region with electrically-connected P+, N+ and P+ regions to enhance its ESD robustness, which is verified in a 0.5-μm (1p2m) 18 V HV CDMOS process. The internal mechanism of the proposed device is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Compared with the conventional LDMOS-DDSCR, the failure current of the compact LDMOS-DDSCR raises from 2.00 A to 4.02 A (increased by 101%), and the trigger voltage reduces from 44.28 V to 39.76 V, without sacrificing layout area. Furthermore, the TLP I-V curves of the proposed LDMOS-DDSCR are measured at different temperatures ranging from 25 °C to 125 °C, which proves its reliability and show potential use in the applications of high voltage integrated circuits.

A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

ESD protection circuit for V-band RF applications in a 65nm CMOS technology

To apply radio frequency circuits, nanoscale CMOS technologies are greatly used but this consequence to a thinner gate oxide and silicided drain/source. With this, the electrostatic discharge (ESD) robustness of RF circuits will be much more degraded. Therefore, there is a need for an ESD protection circuit design in RF circuits against ESD damages. In this paper, the proposed ESD protection circuit is presented with concept based silicon-controlled rectifier (SCR) device, two diodes, PMOS transistor and an inductor to efficiently provide protection for radio-frequency (RF) circuits from ESD damages in nanoscale CMOS process. The concept based SCR device is aided with an inductor to provide efficient ESD path discharge to the SCR device. Moreover, the inductor is used to resonate out the parasitic capacitance generated by the ESD protection circuit at the preferred frequency. In addition, the proposed ESD protection circuit is implemented to a low noise amplifier (LNA) at 60-GHz frequency within an efficient area. Furthermore, the ESD protection circuit is simulated to achieve over 2-kV human body model ESD robustness with good RF performances on LNA in 65-nm CMOS technology.

Challenges &amp; Physical Insights Into the Design of Fin-Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection

This paper presents the detailed physical insights into the silicon-controlled rectifier (SCR) phenomena in planar equivalent Fin SCR devices. The complexity and roadblocks for SCR triggering in FinFET technology are explored. Implication of contact silicidation on Fin SCR turn- ON is discussed in detail. Device design approaches are discussed for efficient Fin-enabled SCRs. In this direction, a novel contact engineering scheme in Fin technology is disclosed for improved SCR action. Moreover, a novel Fin SCR is presented, which offers area-efficient electrostatic discharge current carrying capability.

Resistor-Triggered SCR Device for ESD Protection in High-Speed I/O Interface Circuits

In this letter, an on-chip electrostatic discharge (ESD) protection device was proposed for high-speed I/O interface circuits. A resistor-triggered silicon-controlled rectifier device with improved performance was designed and investigated in a nanoscale CMOS process. As verified in a 0.18- $\mu \text{m}$ CMOS process, the proposed design exhibits a lower clamping voltage and low enough overshoot voltage during ESD stress conditions, and lower parasitic capacitance and low enough leakage current during normal circuit operating conditions. Therefore, the proposed design is suitable for ESD protection of high-speed circuits in low-voltage CMOS processes.

Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High- $k$ Metal Gate CMOS Process

To effectively protect integrated circuits from electrostatic discharge (ESD) damage, this letter proposes a silicon-controlled rectifier (SCR) device with low trigger voltage, low leakage current, low parasitic capacitance, and which requires no additional process step. The proposed device uses two metal gates to separate the anode and cathode of the SCR to reduce the leakage current. These two gates are well controlled to trigger the SCR device. The test devices have been implemented and verified in a 28-nm high- $k$ metal gate CMOS process. Experimental results show that the proposed SCR exhibits a low trigger voltage ( 1 kV in human-body-model tests). Based on its good performances during ESD stress and normal circuit operating conditions, the proposed SCR device is very suitable for ESD protection in advanced CMOS processes.

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology**Project supported by the Central Universities Fundamental Research Project (No. ZYGX2015J035) and the Sichuan Science and Technology Support Project (No. 2016GZ0115).

The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the It2 of the HBT trigger SCR is 80% more than that of the MLSCR.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

A set of novel silicon controlled rectifier (SCR) devices’ characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (γ) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2- dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard 0.5-μm 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What’s more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection

The turn-on speed of electrostatic discharge (ESD) protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device (DTSCR) can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p–n–p and n–p–n transistors. Using the variation lateral base doping (VLBD) structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure (VLBD_DTSCR) is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD_DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n–p–n and p–n–p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD_DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.

A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-μm 5-V CMOS Process

Based on good electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) device is used for on-chip ESD protection. The major concern of SCR is the latch-up issue, because of its low holding voltage. Previous papers tried to design latchup-immune SCR devices; however, those devices would cause lower ESD robustness. In this letter, a new latchup-immune and robust SCR device for ESD protection is proposed and verified in a 0.25-μm 5-V CMOS process. Through inserting one additional parasitic bipolar junction transistor into SCR device structure, this new proposed SCR can increase the holding voltage without causing degradation on its ESD robustness.

Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology

An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias.

Novel Capacitance Coupling Complementary Dual-Direction SCR for High-Voltage ESD

A novel capacitance coupling complementary dual-direction silicon-controlled rectifier (SCR) (CCCDSCR) for high-voltage electrostatic discharge protection is proposed and verified in 0.5-μm BCD process. The trigger voltage of CCCDSCR can be adjusted by coupling capacitance to meet different protection requirements. Compared with traditional lateral double-diffusion NMOS, LDSCR, stacked field-oxide device, and stacked low-voltage-triggering SCR devices, the CCCDSCR has appropriate low trigger voltage of 27.3 V, high holding voltage of 24.3 V, and highest figure of merit (FOM) according to our defined FOM.