Silicon Complementary Metal Oxide Semiconductor Research Articles

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

Optimized electrical properties of p-type field-effect transistors based on WSe2 grown at moderate temperatures

Two-dimensional transition-metal dichalcogenides (TMDCs) have been pursued for high-performance logic electronic devices, and compatibility with silicon complementary metal-oxide-semiconductor (CMOS) technology is essential. Thus, high-quality material synthesis at reduced temperature is a key challenge for TMDC integration with the back-end-of-line silicon CMOS. In this work, TMDCs have been synthesized at temperatures down to 450 °C on SiO2/Si substrates via chemical vapor deposition. This work highlights the necessity of improving metal precursor mass flux during the low-temperature synthesis of TMDC films. Improved electrical characteristics of the back-gated p-type field-effect transistors based on monolayer WSe2 exhibit an on-current of 14 μA/μm and subthreshold swing of 200 mV/dec.

Mid-wavelength infrared photoconductive film synthesized from PbSe molecular ink

Metal chalcogenide thin films are used in a wide range of modern technological applications. While vacuum deposition methods are commonly utilized to fabricate the film, solution-based approaches have garnered an increasing interest due to their potential for low-cost, high-throughput manufacturing, and compatibility with silicon complementary metal–oxide–semiconductor processing. Here, we report a general strategy for preparing mid-wavelength infrared (MWIR = 3–5 μm) photoconductive film using a PbSe molecular ink. This ethylenediamine-based ink solution is synthesized using a simple diphenyl dichalcogenide route, and the deposited film, after the sensitization annealing, exhibits a specific detectivity of 109 Jones at 3.5 μm at room temperature. This work represents the demonstration of MWIR-photosensitive semiconductor films prepared using an emerging alkahest-based approach, highlighting a significant research avenue in the pursuit toward low SWAP-C (size, weight, power consumption, and cost) infrared imager development.

Low-Thermal-Budget Ferroelectric Field-Effect Transistors Based on CuInP2S6 and InZnO.

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of ∼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.

Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.

Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n-type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on-chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non-idealities such as drifting references and long-term retention loss is proposed, demonstrating the importance of device-algorithm co-optimization.

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Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform.

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS2) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal-oxide-semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal-organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm2 V-1 s-1. Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

Wafer-Scale Fabrication of CMOS-Compatible Trapping-Mode Infrared Imagers with Colloidal Quantum Dots

Silicon-based complementary metal oxide semiconductor (CMOS) devices have dominated the technological revolution in the past decades. With increasing demands in machine vision, autonomous driving, and artificial intelligence, silicon CMOS imagers, as the major optical information input devices, face great challenges in spectral sensing ranges. In this paper, we demonstrate the development of CMOS-compatible infrared colloidal quantum-dot (CQD) imagers in the broadband short-wave and mid-wave infrared ranges (SWIR and MWIR, 1.5–5 μm). A new device architecture of trapping-mode detectors is proposed, fabricated, and demonstrated with lowered darkcurrents and improved responsivity. The CMOS-compatible fabrication process is completed with two-step sequential spin-coating processes of intrinsic and doped HgTe CQDs on an 8 in. CMOS readout wafer with photoresponse non-uniformity (PRNU) down to 4%, dead pixel rate of 0%, external quantum efficiency up to 175%, and detectivity as high as 2 × 1011 Jones for extended SWIR at 300 K and 8 × 1010 Jones for MWIR at 80 K. Both SWIR images and MWIR thermal images are demonstrated with great potential for semiconductor inspection, chemical identification, and temperature monitoring.

Selective Sensing of Mixtures of Gases with CMOS-SOI-MEMS Sensor Dubbed GMOS

The need to achieve digital gas sensing technology, namely, a technology to sense and transmit gas-enabled digital media, has been recognized as highly challenging. This challenge has motivated the authors to focus on complementary metal oxide semiconductor silicon on insulator micro electro-mechanical system (CMOS-SOI-MEMS) technologies, and the result is a new pellistor-like sensor, dubbed GMOS, with integrated signal processing. In this study, we describe the performance of such sensors for the selective detection of mixtures of gases. The novel key ideas of this study are: (i) the use of the GMOS for gas sensing; (ii) applying the Kalman filter to improve the signal-to-noise ratio; (iii) adding artificial intelligence (AI) with tiny edge approach.

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

Ferroelectric memristor based on Li-doped BiFeO3 for information processing

As a nanoscale semiconductor memory device, a ferroelectric memristor has promising prospects to break through the von Neumann framework in terms of artificial synaptic function, information processing, and integration. This study presents the fabrication of Li0.09Bi0.91FeO3 as the functional layer for a memristor device based on the Si substrate, enabling the integration of silicon complementary metal oxide semiconductor technology. In addition, it exhibits bipolar resistance switching characteristics in a direct current mode and can rapidly achieve stable conductance tunability at higher frequencies through the applied pulse for biosynapse simulation. More importantly, multiple devices are connected into electrical circuits to realize storage functions with information processing and programmable characteristics. This work paves the way for near-future applications of ferroelectric memristors in information processing.

Ultrafast silicon threshold circuitry for chaotic laser time series

Photonic computing has been intensively studied to explore the ultrahigh bandwidth of lightwaves. However, electronic support is indispensable for the post-processing and control of photonic systems owing to the difficulties encountered in all-optical processing. Herein, we demonstrate an ultrafast silicon circuitry capable of conducting thresholding operations on incoming chaotically oscillating high-bandwidth signals. Such circuits are critical elements in ultrafast random-number generators and photonic reinforcement learning that exploit chaotically oscillating time series. The circuit design, including active inductors for bandwidth expansion, and proof-of-principle fabricated device operations are demonstrated using a 180 nm silicon complementary metal–oxide–semiconductor technology node.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type.Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system.Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials.The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.

Deep Learning-Assisted Enhanced Fano Resonances in Symmetry-Breaking SOI Metasurface

Metasurfaces analogues of Fano resonances provide a powerful platform for high sensitivity sensing, nonlinear optics, and light manipulation. However, previous Fano-resonant metasurfaces usually are not compatible with silicon complementary metal-oxide semiconductor circuits due to their hybrid material structures and large non-radiative loss. Herein, we theoretically demonstrate a silicon-on-insulator metasurface (SOIM) enhancing Fano resonances by using a tandem neural network design. Multiple Fano resonances with high Q-factor have been observed in the symmetry-breaking SOIM. The Fano-resonant mechanism of the SOIM is analyzed. Additionally, the spectral features of the Fano-resonant SOIM as a function of the symmetry tuning factor of the double silicon nanobars and the environment refractive index are also investigated. The result shows that the Fano-resonant SOIM as a methanol sensor with a sensitivity of 310 nm/RIU can achieve an overall figure of merit of 195 in the near-infrared spectral regime. The designed Fano-resonant SOIM shows enormous potential applications in highly sensitive sensors and light-matter interaction enhancement.

Visible‐Blind ZnMgO Colloidal Quantum Dot Downconverters Expand Silicon CMOS Sensors Spectral Coverage into Ultraviolet and Enable UV‐Band Discrimination

Selective spectral detection of ultraviolet (UV) radiation is highly important across numerous fields from health and safety to industrial and environmental monitoring applications. Herein, a nontoxic, visible-blind, quantum dot (QD)-based sensing scheme that expands the spectral coverage of silicon complementary metal-oxide-semiconductor (CMOS) sensors into the UV, enabling efficient UV detection without affecting the sensor performance in the visible and UV-band discrimination, is reported. This scheme uses zinc magnesium oxide (ZnMgO) QDs with compositionally tunable absorption across UV and high photoluminescence quantum yield in the visible. The efficient luminescence and large Stokes shift of these QDs are exploited herein to act as an efficient downconverting material that enhances the UV sensitivity of Si-photodetectors (Si-PDs). A Si-PD integrated with the QDs results in a ninefold improvement in photoresponsivity from 0.83 to 7.5mA W-1 at 260nm. Leveraging the tunability of these QDs, a simple UV-band identification scheme is further reported, which uses two distinct-bandgap ZnMgO QDs stacked in a tandem architecture whose spectral emission color depends on the UV-band excitation light. The downconverting stack enables facile discrimination of UV light using a standard CMOS image sensor (camera) or by the naked eye and avoids the use of complex optics.

Differential nonlinear photocarrier radiometry for characterizing ultra-low energy boron implantation in silicon

The measuring of the depth profile and electrical activity of implantation impurity in the top nanometer range of silicon encounters various difficulties and limitations, though it is known to be critical in fabrication of silicon complementary metal–oxide–semiconductor (CMOS) devices. In the present work, SRIM program and photocarrier radiometry (PCR) are employed to monitor the boron implantation in industrial-grade silicon in an ultra-low implantation energy range from 0.5 keV to 5 keV. The differential PCR technique, which is improved by greatly shortening the measurement time through the simplification of reference sample, is used to investigate the effects of implantation energy on the frequency behavior of the PCR signal for ultra-shallow junction. The transport parameters and thickness of shallow junction, extracted via multi-parameter fitting the dependence of differential PCR signal on modulation frequency to the corresponding theoretical model, well explain the energy dependence of PCR signal and further quantitatively characterize the recovery degree of structure damage induced by ion implantation and the electrical activation degree of impurities. The monitoring of nm-level thickness and electronic properties exhibits high sensitivity and apparent monotonicity over the industrially relevant implantation energy range. The depth profiles of implantation boron in silicon with the typical electrical damage threshold (Y ED) of 5.3 × 1015 cm−3 are evaluated by the SRIM program, and the determined thickness values are consistent well with those extracted by the differential PCR. It is demonstrated that the SRIM and the PCR are both effective tools to characterize ultra-low energy ion implantation in silicon.

Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

Complementary Driving between 2D Heterostructures and Surface Functionalization for Surpassing Binary Logic Devices.

Recently, for overcoming the fundamental limits of conventional silicon technology, multivalued logic (MVL) circuits based on two-dimensional (2D) materials have received significant attention for reducing the power consumption and the complexity of integrated circuits. Compared with the conventional silicon complementary metal oxide semiconductor technology, new functional heterostructures comprising 2D materials can be readily implemented, owing to their unique inherent electrical properties. Furthermore, their process integration does not pose issues of lattice mismatch at junction interfaces. This facilitates the realization of new functional logic gate circuit configurations. However, the reported three-valued NOT gates (ternary inverters) based on 2D materials require stringent operating conditions and complex fabrication processes to obtain three distinct logic states. Herein, a general structure of MVL devices based on a simple series connection of 2D materials with partial surface functionalization is demonstrated. By arranging three 2D materials exhibiting p-type, ambipolar, and n-type conductivities, ternary inverter circuits can be established based on the complementary driving between 2D heterotransistors. This ternary inverter circuit can be further improved for quaternary inverter circuits by controlling the charge neutral point of partial ambipolar 2D materials using surface functionalization, which is an effective and nondestructive doping method for 2D materials.

Extreme‐Angle Silicon Infrared Optics Enabled by Streamlined Surfaces

Infrared optical systems are indispensable in almost all domains of society, but their performances are often restricted by bulky size, small field of view, large thermal sensitivity, high fabrication cost, etc. Here, based on the concept of catenary optics, a novel isophase streamline optimization approach is leveraged to design silicon complementary metal-oxide-semiconductor (CMOS)-compatible metasurfaces with broadband, wide-angle, and high-efficiency performances, which breaks through the glass ceiling of traditional optical technologies. By using the truly local geometric phase, a maximum diffraction efficiency approaching 100% is obtained in ultrawide spectral and angular ranges. Somewhat surprising results are shown in that wide-angle diffraction-limited imaging and laser beam steering can be realized with a record field of view up to 178°. This methodology is scalable to the entire optical band and other materials, enabling unprecedented compact infrared systems for surveillance, unmanned vehicles, medical science, etc.

Relationship between ion track characteristics and single event transients in nanometer inverter chain

Ions with the same linear energy transfer (LET) value, but different energies and species have various ion track characteristics, and thus induce different single event transient (SET) responses in combinational logics. As the technology feature size shrinks, this issue continues to be serious. The research of the relationship between ion track characteristics and SETs in the nanometer combinational logic circuits is of great significance for accurately predicting the soft error rates of nanometer devices used in spacecraft. The combinational logic circuit investigated in this paper is a 65 nm bulk silicon complementary metal oxide semiconductor (CMOS) technology inverter chain. The three-dimensional TCAD model of the inverter chain is established, and the particle transport program for the ion track in bulk silicon is developed by Geant4. The track characteristics of high- and low-energy ions (the energy of low-energy ions is less than 10 MeV·n&lt;sup&gt;–1&lt;/sup&gt;, the energy of high-energy ions ranges from tens of MeV·n&lt;sup&gt;–1&lt;/sup&gt; to hundreds of MeV·n&lt;sup&gt;–1&lt;/sup&gt;) which have the same LET value are compared with each other. Based on the coupled simulation of TCAD and Geant4, the difference in SET pulse widths, induced by ions with the same LET value but different energies, are investigated. It is found that when the energy per nucleon ratio of high-energy ion to low-energy ion increases, the difference in electron-hole pair densities near the center axis of the ion track is more significant, and thus the difference in SET pulse widths is larger. If the energy per nucleon ratio is similar, raising the LET value of ions can increase the difference in electron-hole pair densities on the same radial scale of the ion tracks, and make the SET pulse width difference more obvious. For the high- and low-energy ions with the same LET value, the single event charge generations are different. On the other hand, the change of the ion incident angle results in different charge collections. The coupling of these two factors makes the difference in SET pulse widths dependent on the incident angle of ions. In addition, the influence of ion track characteristics on SET has a weak correlation with the bias voltage of the inverter chain.