The cubic polytype (3C-) of silicon carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the wide band gap characteristics make it an excellent choice for power metal oxide semiconductor field effect transistors (<small>mosfet</small>s). It can be grown on silicon (Si) substrates which is itself advantageous. However, the allowable annealing temperature is limited by the melting temperature of Si. Hence, devices making use of 3C-SiC on Si substrate technology suffer from poor or even almost negligible activation of the p-type dopants after ion implantation due to the relatively low allowable annealing temperature. In this article, a novel process flow for a vertical 3C-SiC-on-Si <small>mosfet</small> is presented to overcome the difficulties that currently exist in obtaining a p-body region through implantation. The proposed design has been accurately simulated with technology computer-aided design process and device software. To ensure reliable prediction, a previously validated set of material models has been used. Further, a channel mobility physics model was developed and validated against experimental data. The output characteristics of the proposed device demonstrated promising performance, what is potentially the solution needed and a huge step toward the realization of 3C-SiC-on-Si <small>mosfet</small>s with commercially grated characteristics.