Silicon Carbide On Insulator Research Articles

Demonstration of SiC-on-Insulator Substrate with Smart Cut™ Technology for Photonic Applications

Silicon-carbide-on-insulator (SiCOI) is a promising platform for photonic integrated circuits. However, the development of this new photonic platform is hindered by the lack of high-quality commercial SiC-on-insulator substrates. In this study, we present a demonstration of the transfer of a single crystalline semi-insulating 4H-SiC thin film on a SiO2 insulated substrate at 150 mm wafer scale using the Smart Cut™ technology. We describe the development of SiCOI substrates and their characterization at each key step of the process. In particular, we provide a detailed study of bow compensation related to the implanted SiC donor substrate. The quality of the transferred SiC layer was investigated as a function of the final annealing temperature applied. The optical indices of the bulk SiC were measured using spectroscopic ellipsometry, and an advanced model has been used to take into account the strong birefringence of the silicon carbide film. Finally, simulations were conducted to design a preliminary set of basic and advanced photonic devices.

Investigations on the Recovery of the Electrical Properties of Smart Cut™-Transferred SiC Thin Film Using SiC-on-Insulator Structures

SiC-on-Insulator (SiCOI) structures fabricated using the Smart Cut™ technique can be of great interest in order to probe the properties of a silicon carbide (SiC) transferred layer, by electrically insulating it from the receiver substrate. In this study, we report the fabrication of such a SiCOI structure using a SiC receiver, as well as its electrical and TEM characterization after high temperature annealing. We highlight a decrease of the transferred layer electrical resistivity with increasing annealing temperature, due to doping reactivation and electron mobility enhancement. After low temperature annealing (1200°C to 1400°C), deep acceptor levels, possibly located in a damaged region near the substrate’s surface, might be responsible of a non negligible electrical compensation. Beyond 1400°C however, the transferred SiC crystal is healed and electron transport is only subjected to shallow nitrogen ionization.

Strong third-order nonlinearity in amorphous silicon carbide waveguides.

Silicon carbide (SiC) photonic integrated platform has attracted significant research interest for on-chip optical applications, owing to its exceptional optical properties such as a broad transparency window, high refractive index, and strong nonlinearity. Among the various types of SiC, amorphous SiC (a-SiC) has particularly emerged as an accessible choice for forming thin-film SiC-on-insulator (SiCOI) stacks, demonstrating promising capabilities for wafer-scale photonic applications. In this work, we prepare three a-SiCOI samples using the plasma-enhanced chemical vapor deposition, with different refractive indices. We fabricate optical waveguides, conduct four-wave mixing measurements, and characterize the nonlinear refractive index in these samples. Our findings reveal that an increase in the refractive index of a-SiC leads to a corresponding increase in the nonlinear refractive index, which is comparable to that of silicon. Hence, a-SiC offers an approach to develop a SiC platform with a wider bandgap than that of silicon, minimizing two-photon absorption while also providing a higher refractive index and stronger nonlinearity compared to crystalline SiC.

SiC-on-insulator based lateral power device and it’ s analytical models

This paper proposes the concept of SiC-on-insulator (SiCOI) lateral power device and its analytical models. The SiCOI technology provides dielectric isolation and improves the vertical breakdown. The analytical models provide the physic insight of the surface potential and electric field distributions for both full and partial depletion cases. The optimal breakdown voltage and doping concentration are deduced to analyze the breakdown mechanism qualitatively. The specific on-resistance in the drift region was also calculated to analyze the conduction characteristics. The influences of the structure parameters on the performances of the SiCOI lateral power device are investigated by the analytical model and numerical simulation. The analytical results of the proposed model are well agreement with the numerical results, confirming the validity of the proposed unified analytical model. Both the analytical and numerical results provide the physical explanation and effective solution for optimizing the electric field and improving breakdown voltage for the SiCOI lateral power device.

Simulation on continuous-wave silicon carbide Raman laser pumped by 1550 nm lasers

We present a detailed simulation-based analysis of continuous-wave (CW) Raman laser in silicon carbide (SiC) waveguide based on SiC-on-insulator (SiCOI). Both Fabry–Perot (FP) cavity and ring-resonator configurations were designed for Raman lasing, which are pumped by 1550 lasers. According to the Raman coupled wave equation, for FP cavity Raman laser, the relations between laser output performances and key parameters such as output reflectivity, waveguide length, and pump power had been systematically analyzed. Similarly, the effects of ring length, coupling coefficient, and coupler position on the output performance were also investigated based on the ring resonator. The results demonstrate the significant potential of near-infrared Raman lasing from SiC. It provides theoretical guidance for the experimental design of the on-chip SiC Raman laser.

Fabrication of SiC-on-Insulator (SiCOI) Layers by Chemical Vapor Deposition of 3C-SiC on Si-in-Insulator Substrates at Low Deposition Temperatures of 1120 °C

Compared to bulk silicon carbide (SiC) wafers, SiC-on-insulator (SiCOI) substrates enable new device designs of electronic switches as well as novel photonic applications. One application is a micro-resonator for the usage in a Kerr frequency comb. For SiCOI substrates, a deposition temperature below 1200 °C is advisable due to stability reasons of the buried oxide layer during chemical vapor deposition (CVD) process conditions. To create 3C-SiC-on-insulator layers, a cold-wall CVD reactor was utilized, with propane and silane as the sources for carbon and silicon, respectively. To improve the cracking of the carbon source gas at low temperatures, the inner setup of the utilized cold-wall CVD reactor was changed to a non-water-cooled system. The change of the inner reactor setup was investigated numerically, and the grown epitaxial layers were characterized by Raman, EDX, SEM-imaging and XRD spectroscopy. We demonstrate successful deposition of 3C-SiC epitaxial layer substrates at temperatures below 1200 °C without delamination on SOI.

Racetrack microresonator based electro-optic phase shifters on a 3C silicon-carbide-on-insulator platform.

We report, to the best of our knowledge, the first demonstration of integrated electro-optic (EO) phase shifters based on racetrack microresonators on a 3C silicon-carbide-on-insulator (SiCOI) platform working at near-infrared wavelengths. By applying DC voltage in the crystalline axis perpendicular to the waveguide plane, we have observed optical phase shifts from the racetrack microresonators whose loaded quality ($ Q $) factors are $\sim\! {30,\!000}$. We show voltage-length product (${{V}_{\pi}} \cdot {{L}_{ \pi}}$) of ${118}\;{{\rm V}\cdot{\rm cm}}$, which corresponds to an EO coefficient ${{r}_{41}}$ of 2.6 pm/V. The SiCOI platform can be used to realize tunable silicon carbide integrated photonic devices that are desirable for applications in nonlinear and quantum photonics over a wide bandwidth that covers visible and infrared wavelengths.

Precision Deep Reactive Ion Etching of Monocrystalline 4H-SiCOI for Bulk Acoustic Wave Resonators with Ultra-Low Dissipation

Integrated mechanical resonators with high quality factors (Q) made in high acoustic velocity materials are essential for a wide range of applications, including chemical sensors, timing resonators, and high-performance inertial sensors for navigation in GPS-occluded environments. While silicon is the most popular substrate for the implementation of microelectromechanical systems (MEMS) resonators, SiC exhibits an exceptionally small intrinsic phononic dissipation due to its low Akhiezer damping limit. This paper reports on the latest developments of precision deep reactive ion etching (DRIE) of monocrystalline 4H SiC-on-Insulator (SiCOI) substrates with the aim to fully take advantage of the exquisite mechanical properties of crystalline SiC. To wit, capacitive Lamé mode micromechanical resonators exhibit ƒ·Q products beyond 1 × 1014 Hz independent of crystalline orientation. The contribution of surface roughness to dissipation and practical considerations to etch mirror-polished trenches in SiCOI substrates are discussed, paving the way towards micromechanical monocrystalline SiC resonators with Qs beyond 100 Million.

(Invited) Nano-Precision Deep Reactive Ion Etching of Monocrystalline 4H-SiCOI for Bulk Acoustic Wave Resonators with Ultra-Low Dissipation

Integrated mechanical resonators with high quality factors (Q) made in high acoustic velocity materials are essential for a wide range of applications, including chemical sensors, timing resonators, and high-performance inertial sensors for navigation in GPS-occluded environments. While silicon is the most popular substrate for implementation of microelectromechanical systems (MEMS) resonators, SiC exhibits an exceptionally small intrinsic phononic dissipation due to high Akhiezer limits. This paper reports the latest results on nano-precision deep reactive ion etching (DRIE) of monocrystalline 4H SiC-on-Insulator (SiCOI) substrates to explore dissipation limits of bulk acoustic wave (BAW) SiC resonators. We report for the first time on capacitive Lamé mode resonators with ƒ·Q products beyond 1×1014 Hz. The contribution of surface roughness to dissipation and practical considerations to etch mirror-polished trenches in SiCOI substrates are discussed, paving the way towards micromechanical SiC resonators with Qs beyond 100 M.

4H-SiC microring resonators for nonlinear integrated photonics.

We demonstrate enhanced four-wave mixing (FWM) in high-quality factor, high-confinement 4H-SiC microring resonators via continuous-wave FWM. With the large power buildup effect of the microring resonator, -21.7 dBFWM conversion efficiency is achieved with 79mW pump power. Thanks to the strong light confinement in SiC-on-insulator (SiCOI) waveguides with submicrometer cross-sectional dimensions, a high nonlinear parameter wγ of 7.4±0.9 W-1 m-1 is obtained, from which the nonlinear refractive index (n2) of 4H-SiC is estimated to be (6.0±0.6)×10-19 m2/W at the telecom wavelengths. Besides, we are able to engineer the dispersion of a SiCOI waveguide to achieve 3dB FWM conversion bandwidth of more than 130nm. This work represents a step toward enabling all-optical signal processing functionalities using highly nonlinear SiCOI waveguides.

High-Q integrated photonic microresonators on 3C-SiC-on-insulator (SiCOI) platform.

We report a high-quality 3C-silicon carbide (SiC)-on-insulator (SiCOI) integrated photonic material platform formed by wafer bonding of crystalline 3C-SiC to a silicon oxide (SiO2)-on-silicon (Si) substrate. This material platform enables to develop integrated photonic devices in SiC without the need for undercutting the Si substrate, in contrast to the structures formed on conventional 3C-SiC-on-Si platforms. In addition, we show a unique process in the SiCOI platform for minimizing the effect of lattice mismatch during the growth of SiC on Si through polishing after bonding. This results in a high-quality SiCOI platform that enables record high Qs of 142,000 in 40 µm radius SiC microring resonators. The resulting SiCOI platform has a great potential for a wide range of applications in integrated optics, including nonlinear optical devices, quantum optical devices, and high-power optical devices.

SiC Wafer Bonding and Deep Reactive Ion Etching Towards High-Aspect Ratio SiC MEMS Fabrication

Recent advances in SiC substrate quality and in the development of high aspect ratio reactive ion etching of SiC microstructures [1] have increased SiC fabrication feasibility and its potential for adaption in scalable optoelectronics [2] and microelectromechanical systems (MEMS). SiC is a wide band gap semiconductor that is suitable for high-power, high-temperature, highly reactive and mechanically strenuous environments. While the ability of SiC to withstand extreme conditions is desirable for harsh applications, it is this same durability that instigates restrictions or difficulties in SiC processing that are not present for Si; however, such process challenges do not outweigh the benefits of SiC. This work specifically tackles the processing challenges for SiC MEMS based on semiconductor-on-insulator structures. The importance of this topic can be viewed through the success of silicon-on-insulator (SOI); SOI wafers expanded the versatility of Si technology by enabling devices with increased switching speed and increased radiation hardness [3] as well as a platform for MEMS devices [4]. In the same vein, silicon carbide-on-insulator (SiCOI) wafers cast an even wider net, enabling SiC MEMS technology that leverages standard Si-based bulk micromachining processes [5] to produce unique device performance [6] and releasable microstructures [7]. However, in progressing towards monolithic SiC MEMS, feasible SiC wafer bonding techniques along with deep etching of high aspect ratio SiC microstructures is still needed to level the playing field between Si and SiC processing capabilities. In this work, the use of Si is avoided entirely and a high-yield wafer bonding and etch process of SiC/Insulator/SiC stacks is presented. The replacement of Si with SiC as a handle wafer allows for the design of all SiC-based MEMS devices for high shock resistant and temperature applications. The fabrication process begins with a thorough cleaning of 4H-SiC wafers followed by SiO2 deposition with a tetraethyl orthosilicate (TEOS) precursor via low-pressure chemical vapor deposition (LPCVD) at 750 °C. The oxide covered wafers were annealed to 1100 °C for 2 hours to densify and outgas the oxide. The SiO2 (up to 4 µm) on the Si-face was then chemically mechanically polished down to a final thickness of 3 µm thickness and a root-mean squared (RMS) roughness < 0.5 nm suitable for bonding (Figure 1). Prior to bonding, the wafers undergo additional cleaning processes to ensure a clean bonding interface. Direct wafer bonding of the Si faces of two SiC wafers was achieved in a class-100 cleanroom using a modified plasma bonding technique. The bonding was initiated by applying a local force to the center of the aligned wafers; the bond then propagates from the center to the wafer edge. Additionally, a post bond anneal at 1100 °C was used to achieve fusion strength. The bonded SiC wafers were electroplated with 1.7 - 2 μm Ni hard mask [1] and then diced into 10 mm x 10 mm coupons for anti-bosch etch experiments to produce deep SiC trenches [8]. An anti-bosch process describes a recipe that alternates between two SF6/O2 segments; one segment is designed to etch SiC, while the other segment is designed to remove sidewall passivation. This is contrary to the well-established Bosch process for Si which uses one segment to etch Si and the other to passivate the sidewalls. The anti-bosch process for SiC was designed to etch through the device layer and stop on the buried oxide; after which, the hard mask and seed metals were removed. Lastly, the etched microstructures were released with vapor hydrofluoric acid (HF). Figure 2 summarizes the process flow and Figure 3 shows the etch results achieved on 4H-SiC and 4H-SiC/SiO2/4H-SiC samples. The efficacy of the outlined process is demonstrated through successful actuation of fabricated structures (Figure 4). Overall, this work demonstrates a process for effective SiC wafer bonding and SiC etching in the presence of buried oxide in order to fabricate high-aspect ratio SiC MEMS. [1] L.E. Luna, et al. ECS J. Solid State Sci. Technol. 6, p. 207 (2017). [2] J.D. Caldwell, et al. Nano Lett. 13, p. 3690 (2013). [3] G.K. Celler and S. Cristoloveanu, J. Appl. Phys. 93, p. 4955 (2003). [4] E. Cook, et al. Solid-State Sensors, Actuators and Microsystems Workshop, June 2018. [5] R. Candler, et al. IEEE Transactions on Advanced Packaging 23, p. 227 (2003). [6] H-I. Kuo, et al. Proceedings of Transducers, Boston, MA, p. 742 (2003) [7] H.A. Moghadam, A. A. Orouji, A. Dideban, Semicond. Sci. Technol. 27, 015001 (2012). [8] L.E. Luna, et al. J. Micromech. Microeng. 27, 095004 (2017). Figure 1

Formation of silicon carbide nanowire on insulator through direct wet oxidation

Silicon carbide on insulator is a promising platform for electronic devices at high temperature as well as for opto-electrical applications. Utilizing the chemical inertness of SiC, this work presents a novel technique to form cubic-silicon carbide (3C-SiC) on silicon dioxide (SiO2) by using silicon wet-thermal-oxidation. Experimental data confirmed that SiO2 was successfully formed underneath of 300nm width SiC nanowires, while the properties of SiC was almost unaffected during the oxidation process. This simple technique will open the pathway to the development of SiCOI (SiC on insulator) based electrical and optical applications.

Transferrable single crystalline 4H-SiC nanomembranes

In this work, we demonstrate a transferrable single crystalline 4H-SiC nanomembrane (SiC NM) released from a SiC-on-insulator (SiCOI) wafer.

Graphene as a Buffer Layer for Silicon Carbide-on-Insulator Structures

We report an innovative technique for growing the silicon carbide-on-insulator (SiCOI) structure by utilizing polycrystalline single layer graphene (SLG) as a buffer layer. The epitaxial growth was carried out using a hot-mesh chemical vapor deposition (HM-CVD) technique. Cubic SiC (3C-SiC) thin film in (111) domain was realized at relatively low substrate temperature of 750 °C. 3C-SiC energy bandgap of 2.2 eV was confirmed. The Si-O absorption band observed in the grown film can be caused by the out-diffusion of the oxygen atom from SiO2 substrate or oxygen doping during the cleaning process. Further experimental works by optimizing the cleaning process, growth parameters of the present growth method, or by using other growth methods, as well, are expected to realize a high quality SiCOI structure, thereby opening up the way for a breakthrough in the development of advanced ULSIs with multifunctionalities.

STM OBSERVATION OF GRAPHENE FORMATION USING SiC-ON-INSULATOR SUBSTRATES

We used scanning tunneling microscopy to investigate graphene formation on an SiC -on-insulator (SiC-OI) substrate. Annealing of an SiC-OI substrate with an SiC thickness of 1500 nm produced a graphene layer on the SiC surface. When the thickness of the SiC film was 5 nm, a graphene layer was not formed on the SiC surface. However, after annealing a C-covered SiC-OI substrate with an SiC thickness of 5 nm, a graphene layer formed on the SiO2 surface.

Electrical Characteristics of MOSFETs Using 3C-SiC with Buried Insulating Layer

Metal oxide semiconductor field effect transistors (MOSFETs) using SiC on insulator (SiC-OI) substrate with the structure of 3C-SiC (100)/SiO2/Si have been fabricated. SiC-OI substrates with SiC thicknesses of 100 nm and 600 nm are employed as starting materials and aluminum ions are implanted for p-regions or channel regions with a multi-implantation technique. Afterward, to form the source and drain regions, phosphorus ions are implanted. The gate oxide layer is grown in dry thermal oxidation, followed by post-oxidation annealing. Nickel is used as a contact material for the source and drain region, and aluminum is used for the gate material. From Id-Vd characteristics, 600 nm SiC-OI MOSFET is superior to 100 nm SiC-OI MOSFET. It is might that the crystalline quality of surface SiC layers affects the performance of MOSFET. SiC-OI MOSFET is operated successfully for the first time.

Optical properties revealing annealing behavior of high-temperature He-implantation induced defects in silicon carbide

6H-SiC single crystal specimens were implanted at 600 K with 100 KeV He ions to three successively increasing fluences and subsequently annealed at different temperatures ranging from 600℃ to 1200℃ in vacuum. After the annealing, the samples were investigated by using Raman scattering spectroscopy and photoluminescence spectrometry，respectively. Both of the two methods showed that the damage induced by helium-ion-implantation in the lattice is closely related to the dose. The thermal annealing brings about recovery of the damage，and different levels of damage require different annealing temperature to recover efficiently. It is indicated that different annealing stages involve different mechanisms，corresponding to recombination of point defects，formation of He-vacancy complexes，and nucleation and coarsening of bubbles，respectively. The experimental results indicate that high temperature implantation is an effective way to avoid amorphization of the implanted layer due to damage accumulation. Helium implantation can be used to introduce buried nanoscale cavities as the nucleation site for the buried oxide in a well defined region proposed for an alternative and more economical method of manufacturing SiC-on-Insulator （SiCOI）.

Epitaxial Growth of SiC on Silicon on Insulator Substrates with Ultrathin Top Si Layer by Hot-Mesh Chemical Vapor Deposition

The epitaxial growth of SiC on silicon-on-insulator (SOI) substrates with an ultrathin (<10 nm) top Si layer by hot-mesh chemical vapor deposition (CVD) was investigated. This method utilizes heated tungsten wires arranged in a mesh, which promotes the high decomposition efficiency of H2 gas. Using the hot-mesh CVD method, SiC epitaxial films were successfully grown on SOI substrates without voids being formed, which are formed readily in thin (<100 nm) top Si layers at temperatures above 800 °C. Some micropatterns for micro-electro-mechanical systems were fabricated on SiC on insulator (SiCOI) structure substrates by reactive ion etching and wet etching.

Characterization of Si1-xCx:H thin films deposited by PECVD for SiCOI heterojuntion fabrication

The SiC-on-insulator (SiCOI) heterojuntion is interesting for high temperature, high power, high frequency, smart-sensors, and micromechanical applications, due to the combined SiC and Si substrate advantages. In this work we investigate the properties of amorphous hydrogenated silicon carbide thin films (a-Si1-xCx:H) deposited by PECVD onto silicon and silicon covered with an insulator layer, before and after thermal annealing processing aiming crystallization of the deposited films. Due to their great interest for optoelectronic applications, four different insulator materials are investigated: high temperature (1100 ºC) thermal SiO2, low temperature (320 ºC) PECVD SiO2, SiOxNy, and Si3N4. The infrared absorption studies for as-deposited films show that films grown onto silicon covered with Si3N4 layer have a better coordination among Si and C atoms. Post-growth thermal annealing leads to the crystallization of the material for all the studied amorphous films. Raman measurements exhibited C-C bond vibration bands, after annealing, only for films deposited onto PECVD insulator. XRD results showed that films deposited on thermal-SiO2/Si(100) and Si(100) substrates have also a preferential (100) crystalline orientation, while films deposited on PECVD-insulator/Si(100) present a broad band associated with H-SiC(10L) and 3C-SiC(111) diffractions.