Silicon Carbide On Insulator Research Articles

Bonding characteristics of 3C-SiC wafers with hydrofluoric acid for high-temperature MEMS applications

This paper describes the bonding characteristics of 3C-SiC wafers using plasma enhanced chemical vapor deposition (PECVD) oxide and hydrofluoric acid (HF) treatment for SiC-on-insulator (SiCOI) structures and high-temperature microelectromechanical system (MEMS) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (0 0 1) wafer by thermal wet oxidation and a PECVD process, successively. The pre-bonding of two polished PECVD oxide layers was made under definite pressure after the treatment of hydrophilic surface activation in HF. The bonding processes were carried out under various HF concentration and external applied pressure. The bonding characteristics were evaluated by the effects of HF concentration used in the surface treatment on the roughness of the oxide and the pre-bonding strength, respectively. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by attenuated total reflection Fourier transformed infrared spectroscopy (ATR-FTIR). The root-mean-square (RMS) surface roughness of the oxidized 3C-SiC layers was measured by atomic force microscope (AFM). The strength of the bonded wafer was measured by tensile strength meter (TSM). The bonded interface was also analyzed by scanning electron microscope (SEM). The values of the bonding strength ranged from 0.52 to 1.52 MPa according to HF concentrations without the external applied load during pre-bonding process. The bonding strength initially increases with increasing HF concentration and reaches the maximum at 2.0% of HF concentration and then decreases. Consequently, low temperature 3C-SiC wafer direct bonding technique using a PECVD oxide layer and HF could be applied as a fabrication process of high quality substrates for high performance electronic devices and harsh environment MEMS applications.

극한 환경 MEMS용 SiCOI 구조 제작

This paper describes on an advanced technology of 3C-SiC/Si(100) wafer direct bonding using PECVD oxide to intermediate layer for SiCOI(SiC-on-Insulator) structure because it has an attractive characteristics such as a lower thermal stress, deposition temperature, more quick deposition rate and higher bonding strength than common used poly-Si and thermal oxide. The PECVD oxide was characterized by ATR-FTIR. The bonding strength with variation of HF pre treatment condition was measured by tensile strength measurement system. After etch-back using TMAH solution, roughness of 3CSiC surface crystallinity and bonded interface was measured and analyzed by AFM, XRD, and SEM respectively.

Smart Cut TM SiCOI wafers for MBE GaN epitaxy

The Smart CutTM technology, now recognised as the technology of choice for the manufacturing of SOI substrates (Silicon On Insulator) [G. G. Shahidi, IBM J. Res. & Dev. 46, No. 2/3 (March and May 2002)], has got the unique potential to propose high quality Compound Semiconductors On Silicon (CSOS) substrates as a complementary technology to epitaxy. The use of this technology has led to the development of SiCOI (SiC On Insulator) structures where a thin film of single SiC crystal is bonded onto an oxidized substrate such as, for instance, a silicon substrate [L. Di Cioccio et al., Mater. Sci. Eng. B 46, 349 (1997)]. In this paper, we present the recent developments of SiCOI substrates developed using the Smart CutTM technology as well as the first results of GaN epitaxy performed onto these new structures. As a proof of concept and demonstration of feasibility, a Molecular Beam Epitaxy (MBE) GaN layer has been grown onto SiCOI substrate small samples and has been compared with similar growth on SiC bulk substrate. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Heterogeneous silicon integration by ultra-high vacuum wafer bonding

Heterogeneous integration of technologically important materials, such as SiC/Si, GaN/Si, Ge/Si, Si/nano-Si/Si, SiC-on-insulator (SiCOI), and ZrO2/SiO2/Si, was successfully made by ultra-high vacuum (UHV) wafer bonding. A unique, UHV bonding unit, especially designed to control interface structure, chemistry, and crystallographic orientation within narrow limits, was used to produce homophase and heterophase planar interfaces. In-situ thin-film-deposition capability in conjunction with the wafer bonding offered even more flexibility for producing integrated artificial structures. Prebonding surface preparation was critically important for the formation of strong bonded interfaces. The substrate-surface morphology was examined by atomic-force microscopy (AFM) prior to bonding. In-situ Auger spectroscopy measurements of surface chemistry were invaluable predictors of bonding behaviors. Plasma processing very effectively cleaned the substrates, achieving a near-perfect interfacial bond at the atomic scale. The integrity of the bonded interfaces was studied in the light of their structural and chemical characteristics analyzed by high-resolution, analytical electron microscopy.

극한 환경 MEMS용 2" 3C-SiC기판의 직접접합 특성

This paper describes on characteristics of 2" 3C-SiC wafer bonding using PECVD (plasma enhanced chemical vapor deposition) oxide and HF (hydrofluoride acid) for SiCOI (SiC-on-Insulator) structures and MEMS (micro-electro-mechanical system) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR (attenuated total reflection Fourier transformed infrared spectroscopy). The root-mean-square suface roughness of the oxidized SiC layers was measured by AFM (atomic force microscope). The strength of the bond was measured by tensile strength meter. The bonded interface was also analyzed by IR camera and SEM (scanning electron microscope), and there are no bubbles or cavities in the bonding interface. The bonding strength initially increases with increasing HF concentration and reaches the maximum value at 2.0 ％ and then decreases. These results indicate that the 3C-SiC wafer direct bonding technique will offers significant advantages in the harsh MEMS applications.ions.

3C-SiC modulator for high-speed integrated photonics

ABSTRACTWe propose a compact 3C-SiC electro-optic modulator for high-speed Si-based integrated optoelectronics operating at 1.55-μm-wavelength. The device is based on an optical microresonator using sub-micron size high-index-contrast SiC waveguides on a SiC-SiO2-Si [SiC-on-Insulator (SICOI)] platform. Three different electrode configurations are analyzed. Switching times on the order of tens of ps are predicted by using low bias voltages.

CVD 절연막을 이용한 3C-SiC 기판의 초기직접접합에 관한 연구

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECYD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of 5.3 kgf/cm<TEX>$^2$</TEX>to 15.5 kgf/cm<TEX>$^2$</TEX>.

A New Process for the Fabrication of SiC Power Devices and Systems on SiCOI (Silicon Carbide On Insulator) Substrates

ABSTRACTFeasibility of 4H-SiC epitaxy on SiCOI substrates has been demonstrated, with high quality of obtained layers. Power Schottky diodes were designed and fabricated on these new structures, and exhibited very interesting electrical performance, particularly in reverse mode, with Vbr ∼ 1000 V. This technology is very promising for the realization of monolithic SiC power systems.

A Novel Method of Fabricating SiC-On-Insulator Substrates for Use in MEMS

ABSTRACTThis paper reports on a novel, bonding-free method to fabricate silicon carbide-on-insulator (SiCOI) substrates. The process bypasses wafer bonding by using a high deposition rate polysilicon process in conjunction with wet chemical etching to produce wafer-thick polysilicon layers that serve as substrates for the SiCOI structures. Because wafer bonding is not used, insulators of various material types and thickness can be used. Using this method, transfer percentages over 99% are readily achievable. Various applications could benefit from this technology, including high temperature SiC-based microelectromechanical systems (MEMS) and SiC electronic devices.

Ion beam synthesis of polycrystalline SiC on SiO2 structures forMEMS applications

SiC on insulator for microelectromechanical systems has beendirectly synthesized by high-dose carbon ion implantation of amorphous orpolycrystalline Si on SiO2. For this, a four-step implant process hasbeen defined by TRIM simulation. X-ray diffraction and in-depth Auger electronspectroscopy measurements corroborate the formation of a stoichiometricpolycrystalline SiC layer above the sacrificial oxide. These data demonstratethe ability of the process for the direct synthesis of complex SiC oninsulator (SiCOI) structures. Micromechanical test structures have beenfabricated from these layers, which allowed the comparison of residual stressaccording to the synthesis process of the layers.

Heteroepitaxial growth of 3C-SiC on SOI for sensor applications

Typical industrial high temperature sensor applications are reviewed and a short overview of the different high temperature sensor technologies is given. The pros and cons are weighted. Silicon carbide on insulator (SiCOIN) technology comes out to be the most attractive, provided the state of development can be brought up to the one of silicon and silicon on insulator (SOI). Due to the lack of commercially available SiC on SOI wafers, a new SiC on SOI technology has been developed. It is based on the precursor gas methylsilane. The low temperature growth process is described and in-situ n-type doping, which is necessary for sensor applications, has been carried out successfully over a wide range of concentrations without loosing the good crystal properties. Actually the full process is being transferred from a test reactor to a 4 inch machine. This should provide 3C-SiC on SOI wafers for commercial sensor applications. A demonstrator of combustion pressure sensor dedicated to pressure-based engine control is shown. Results of the pressure sensor fitted in a motor-test setup are summarized.

Si/SiC UHV Direct Wafer Bonded Interface Structure

AbstractPlanar (001)Si/(0001) Si-terminated 6H-SiC interfaces were synthesized by UHV diffusion bonding of cleaned, on-axis and vicinal wafers at 1100°C for 5 hours, at MPa pressure. The interfaces were crystalline up to their defining plane, without nanospectroscopically detectable impurities. The crack opening tests showed the interfaces were stronger than the Si substrates. Oxygen on the substrate surfaces resulted in silicon carbide on insulator (SiCOI) interface formation.

β-SiC films on SOI substrates for high temperature applications

Abstract Single crystalline, cubic β-SiC films were deposited by CREE Inc., USA on bonded SOI wafers. The SiC deposition took place under standard conditions used at CREE for deposition on Si wafers, and at deposition temperatures 25 °C and 50 °C below standard deposition conditions to investigate the influence of the deposition temperature on the damage of the buried oxide layer and therefore the insulating capability of that layer. Transmission electron microscopy (TEM), atomic force microscopy (AFM) and optical microscopy were used for structural analysis of the Silicon Carbide On Insulator (SiCOI) structure. The deposited β-SiC films, the buried SiO2 layer, and the SiC Si interface were investigated. First measurements showed similar results for all three deposition temperatures indicating that the deposition temperature is not the only parameter defining the structural and therefore also the electrical quality of the SiCOI wafers. The electrical measurements were performed up to T = 723 K (current limit of the equipment) and the results showed good electrical insulation of the SiC layer from the Si substrate in the whole temperature range.

Silicon carbide on insulator formation using the Smart Cut process [Note 1

The Smart Cut process has been applied for the first time to SiC, in order to form silicon carbide on insulator (SiCOI) structures. These structures have been formed on polycristalline SiC and on silicon substrates.