Active Silicon Layer Research Articles

Radiation-tolerant dose sensor based on undoped amorphous silicon

Single-crystal silicon diodes are replacing gas-filled dose-rate meters because they are batch-processable, mechanically robust, compact, and operable at low voltages. However, they are prone to radiation damage in high dose fields. Hydrogenated amorphous silicon (a-Si:H) provides the manufacturing and operational benefits of silicon while adding inherent radiation hardness because of its wider bandgap and disordered microstructure. Previously, sensors with tens of micrometers thick a-Si have been investigated for direct dose sensing in x-ray imaging applications. However, the limited charge carrier lifetimes of the medium can reduce the charge collection efficiency and thereby the sensitivity. If a higher density, higher Z active media is coupled to thin amorphous silicon active layers, then an additional indirect component can be added to this direct signal to exhibit ∼15 μGy/s dose-rate sensitivities at zero and low-bias (<0.5 V) operation. Here we show that thin (150, 300, 450 nm) a-Si:H optical sensors can produce external quantum efficiencies above 40% and internal quantum efficiencies that exceed 70 % over a broad band from 380 nm to 650 nm, resulting in dose-rate sensitivity even at 0 V. When the charge-collecting electrodes abutting the a-Si:H serve the dual purpose as reflective layers in a lossy Fabry-Perot cavity, then internal quantum efficiencies greater than 83 % can be realized in a 30 nm thick layer at 410 nm. Cobalt-60 gamma-ray irradiation to 100 kGy (air) shows no radiation-induced degradation for even the thicker 300 nm sample; rather, a radiation hardening effect is observed as evinced in reduced dark current.

Optimizing thin-film silicon solar cells with nanostructured TiO2 and a silver back reflector for enhanced energy conversion efficiency

This paper investigates the improvement of energy conversion efficiency in thin-film silicon solar cells by employing periodic nanostructures of TiO2 on the silicon active layer and a back reflector featuring periodic nanostructures of silver. The objective is to increase the optical path length, enhance absorption probability for longer wavelengths, and subsequently improve solar cell performance. Three silicon-based solar cell configurations are proposed and simulated using the finite difference time domain (FDTD) method to assess their performance. Electrical characteristics are obtained through the drift-diffusion method. The resulting short-circuit current density increased from 40.93 to 65.28 to 95.373mA/cm2 for the three cells, leading to significant improvements in conversion efficiency with observed values of 20.39%, 33.26%, and 47.28%, respectively, in the optimized structures. Furthermore, we compare the simulation results of the three structures with those of a reference structure and several structures previously proposed in the literature.

Improved Performance of Silicon Anodes Using Copper Nanoparticles as Additive

Abstract Nanoscale copper has been successfully integrated into a silicon-based anode via a cost-effective, one-step process. The additive was found to improve the overall electrical conductivity and charge/discharge cycling performance of the anode. Analysis of the new material shows that copper particles are homogeneously interspersed into the silicon active layer. The formation of Cu3Si during the annealing step of the fabrication process was also confirmed using X-ray diffraction and is thought to contribute to the structural stability of the anode during cycling. Despite the inclusion of only small quantities of the additive (approximately 3%), anodes with the added copper show significantly higher initial discharge capacity values (957 mAg−1) compared to anodes without copper (309 mAg−1), and they continue to outperform the latter after 100 charge/discharge cycles. Results also show a significant decrease in the resistance of anodes with the additive, a contributing factor in the improvement of the electrochemical performance.

Initial Nucleation Approach for Large Grain-Size and High-Quality Microcrystalline Silicon Active Layer in Thin Film Transistors

High mobility and stability are critical factors for thin film transistor (TFT) device quality. These parameters are directly dependent on the crystalline structure of the active layer materials. In this paper, the early nucleation approach was performed for increasing the crystalline grain size of microcrystalline silicon (μc-Si:H) active layer for TFT device quality. The crystalline nucleation is delicately regulated in an intense hydrogen plasma environment using the plasma enhanced chemical vapor deposition (PECVD). When compared to μc-Si:H deposition without the nucleation approach, the crystalline volume factor of μc-Si:H increased from 60% to over 80% by using the nucleation technique. The nucleation increases the crystalline grain size by five orders of magnitude. Furthermore, the surface roughness of μc-Si:H is decreased from 13.7 nm to 7.1 nm. A forming-gas post-annealing treatment (≤400 °C) is used to minimize defect density. With a low microstructural factor, thermal-treated film quality improves dramatically. Nucleation approach is to be a simple and efficient for producing high-quality TFT devices.

Optical absorption in roughened silicon photovoltaic module

Photovoltaic current electric generation is directly related to the sunlight absorption in the active layers. The active layer material type and the optical losses remain the principal parameters, which have a greater effect on the amount of this absorption. This study focuses on improving the absorption in the silicon active layer of a silicon photovoltaic module by roughening the rear surface of the silicon layer. According to the Generalized Transfer Matrix Method, we derive the transmission from the incoherent multilayered module structure with a rough surface. We follow the optical model developed by Krauter and Hanitsch to derive the transmission into the silicon layer. Then the absorption is deduced from the difference between the transmission from the module and the transmission into the silicon. The effect of the incidence angles on the absorption is considered for different polarizations of light. The results of this study show a significant enhancement in the absorption in comparison to the absorption of the module with a polished rear surface. The short circuit current generated by the module with a rough rear surface silicon layer obtained is greater than that of the module with a polished rear surface.

High-Efficiency Crystalline Silicon-Based Solar Cells Using Textured TiO2 Layer and Plasmonic Nanoparticles.

A high-efficiency crystalline silicon-based solar cell in the visible and near-infrared regions is introduced in this paper. A textured TiO2 layer grown on top of the active silicon layer and a back reflector with gratings are used to enhance the solar cell performance. The given structure is simulated using the finite difference time domain (FDTD) method to determine the solar cell’s performance. The simulation toolbox calculates the short circuit current density by solving Maxwell’s equation, and the open-circuit voltage will be calculated numerically according to the material parameters. Hence, each simulation process calculates the fill factor and power conversion efficiency numerically. The optimization of the crystalline silicon active layer thickness and the dimensions of the back reflector grating are given in this work. The grating period structure of the Al back reflector is covered with a graphene layer to improve the absorption of the solar cell, where the periodicity, height, and width of the gratings are optimized. Furthermore, the optimum height of the textured TiO2 layer is simulated to produce the maximum efficiency using light absorption and short circuit current density. In addition, plasmonic nanoparticles are distributed on the textured surface to enhance the light absorption, with different radii, with radius 50, 75, 100, and 125 nm. The absorbed light energy for different nanoparticle materials, Au, Ag, Al, and Cu, are simulated and compared to determine the best performance. The obtained short circuit current density is 61.9 ma/cm2, open-circuit voltage is 0.6 V, fill factor is 0.83, and the power conversion efficiency is 30.6%. The proposed crystalline silicon solar cell improves the short circuit current density by almost 89% and the power conversion efficiency by almost 34%.

A Sample Preparation Workflow for Delayering a 45 nm Node Serial Peripheral Interface Module

Abstract Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Light-harvesting enhancement in ultrathin film silicon solar cells using photonic and plasmonic nanostructures

Past few decades, nanostructures are useful in the active region and light-harvesting layers in thin film solar cells. In this work, the high reflectance alternative Si/SiO2 distributed Bragg reflectors (DBRs), and aluminum (Al) thin film layers were integrated as a backside reflectors in ultrathin film silicon solar cells to improve the light trapping mechanism using finite-difference time-domain (FDTD) method. DBR is known as one-dimensional photonic crystal (1DPC) used as backside reflectors with the addition of SiO2 buffer layer. Further, the transverse electric (TE) and magnetic (TM) field distribution shown the strong light scattering in the silicon active layer region by integration of top (ITO) and bottom (Al) nanogratings. Both polarization conditions yielded the highest current density (Jsc) of 22.03 (TE) and 30.42 mA/cm2 (TM) achieved within 50 nm active region thickness.

Optimization of Shape, Size and Material of Plasmonic Nano Particles in Thin Film Solar Cell

In this study we present optimized shape, size and material of plasmonic nanoparticles in thin film solar cell. For this purpose, we chose silicon active layer solar cell, on the top of active layer another layer of silicon dioxide was used as antireflection coating. Thickness of ARC layer was kept 71nm. On the top of ARC layer metallic nanoparticles were placed. Parameters of NP’s such as shape, size and material were varied. Respective variations in the absorption of light in the active silicon layer were observed respectively. Absorption patterns were plotted against wavelength range of 400nm to 1400nm of incident light radiation using Finite Element Method (FEM). Results revealed the most optimized size and shape of nanoparticles that can contribute to the absorption of light in the active layer of the solar cell. Results also distinguished the best material for nanoparticle.

Electrothermal analysis of novel N-P-P FinFET with electrically doped drain: a dual material gate device for reliable nanoscale applications

In this paper, we offer a new structure of N+-P-P Fin Field Effect Transistor (FinFET) with a dual material gate in which the drain side P–N junction has been physically removed. The P-type drain consists of two parts, depletion region (DR) and electrically doped (ED) area, where the ED region is surrounded by an extra gate with optimized length and appropriate work function made of barium (B-gate). The ED region located under the B-gate is converted to N+ drain using the charged plasma (CP) concept to design the CP-FinFET. Improved ability to control the hot carrier effect by amending the critical electric field is the main idea of this work. The p-type depletion region (DR) created between the silicon active layer and electrically doped drain eliminates the gate-drain overlap and reduces the charge sharing and short channel effects (SCE). The modified electric field in the DR region offers advantages including improved hot-electron reliability and high-performance devices. Therefore, in the CP-FinFET the degradation mechanism improves due to the hot carrier effect (HCE) reduction. Indeed, the improvement in device performance is investigated using three-dimensional Atlas simulator with concentrating on the gate current, off-state current, reliability, electron temperature and gate induced drain leakage (GIDL). The comparison results demonstrate the superiority of the proposed structure as a high-efficiency device to design reliable Complementary metal–oxide–semiconductor circuits in nanoscale.

Imaging the native inversion layer under buried oxide in silicon-on-insulator radio frequency device technology via scanning surface photovoltage microscopy

For radio frequency (RF) wireless integrated circuits and devices fabricated on silicon-on-insulator technologies, there has been indirect evidence of the presence of a parasitic native inversion layer, due to an effective trapped charge, “Q+,” at the interface of the buried oxide (BOX) and the underlying high resistivity p-type Si substrate in production level wafers. This inversion layer can have adverse implications for the RF performance of active devices fabricated for use in wireless technologies, notably the “RF switch.” In this study, the authors characterize the complementary-metal-oxide-semiconductor field effect RF transistor used in such a switch. The FET is built on the active epitaxial silicon layer on top of the BOX layer; its purpose is to control input and output RF signals in integrated wireless circuitry. Using scanning surface photovoltage microscopy, the authors present the first data to show quantitatively the extent of this inversion layer into the substrate. They also present device electrical performance data proving the effectiveness of the processes used to suppress the effects of Q+.

Direct Bonding of 4H-SiC and SOI Wafers for Radiation-Hardened Image Sensors

4H-SiC and SOI substrates were bonded by SiO2-SiO2 direct bonding method with diluted HF solution (0.5 wt.%). After the bonding process, the handle layer and the BOX layer of the SOI substrate were etched by TMAH solution, and finally the silicon active layer with a thickness of 1.5 μm was remained on the 4H-SiC substrate. Using this silicon layer, Si photodiodes on 4H-SiC for the radiation hardened image sensors were fabricated and demonstrated.

Performance Evaluation of Innovative Ion-Sensitive Field Effect Diode for pH Sensing

In this paper, we have successfully introduced and characterized an innovative ion sensitive device called “Ion sensitive field effect diode”, a completely new ion-sensitive sensor. In conventional ion-sensitive devices, electrolyte/insulator interface reactions produce a conductive channel between the drain and the source whereas in our proposed structure, a p-n junction forms and is responsible for the conductivity. Since it is for the first time that such device is proposed as an ion sensor, comprehensive characterizations have been performed based on our previously TCAD-based model which was developed to simulate electrolyte and electrolyte/insulator interface. Considering this reliable model, sensing parameters of pH sensors, such as sensitivity and signal to noise ratio are investigated and evaluated. Meanwhile, an accurate model to approximate the noise behavior of the device is proposed. Moreover, the effect of Silicon active layer thickness and doping concentration on the sensitivity of the device has been studied. Results reveal that ion sensitive field effect diode can achieve sensitivity about five times higher than the Nernst limit and can be considered as a promising candidate toward accurate and more sensitive ion sensors and this new type of sensor deserves further attention and development.

An Accurate TCAD-Based Model for ISFET Simulation

In this paper, a new model is successfully introduced to describe an ion-sensitive field-effect transistor in a TCAD tool. To model this device accurately, the model should evaluate surface charge density behavior of electrolyte and insulator interface as well as ion concentration according to different pH values. Performance and accuracy of the model have been examined through assessing parameters such as sensitivity and signal-to-noise ratio (SNR). The effect of silicon active layer thickness on the sensitivity and SNR and its maximum condition and relevance to silicon thickness are investigated. Results show that the model can predict the device responses accurately, in accordance with experimental reports. The proposed model reveals that although the top oxide to buried oxide capacitance ratio does not change the SNR; the silicon active layer thickness can affect it efficiently.

Electrical evaluation of the crystallization characteristics of excimer laser annealed polycrystalline silicon active layer

We showed that the crystallinity of polycrystalline silicon (poly-Si) active layer of low temperature poly silicon (LTPS) devices can be comparatively analyzed through conventional electrical methods. We fabricated the MOS capcitors and the thin film transistors (TFT) with different excimer laser annealing (ELA) crystallization conditions. Through the capcitance–time (C–t) method and the frequency variable capacitance–votage (C–V) method, we detected the influence of grain boundaries of poly-Si. The generation lifetime (τg) and the number of border traps (Nbt) calculated by these methods could detect tiny crystallinity differences related to energy density differences about 10–15 mJ/cm2 during the recrystallization. The field effect mobility (μFE) and off current (Ioff) measured with the TFTs also showed the same tendency. The results of this study show that the measurements using MOS capacitor are sufficiently reliable and suitable for obseving property changes of the poly-Si active layer.

Formula omitted] thin Low Gain Avalanche Detectors (LGAD) for timing applications

LGAD detectors on 300μm thick high resistivity p-type substrates were proposed for the first time by IMB-CNM-CSIC. They are customized Avalanche Photodiodes (APD) to obtain a high electric field region confined close to the reversed junction. Therefore, only electrons generated by an incident particle passing through the detector and drifting to the n+ contact, start the impact ionization process. Thus, the collected charge is multiplied. The basic difference between APDs and LGADs is the gain. LGADs have a moderate gain in order to avoid the inherent problems due to high multiplication: cross talk and high noise. In that way, the detector signal can be kept high without increasing the noise.These devices have been successfully fabricated and extensively characterized, before and after irradiation. Unfortunately, neutron and proton radiation cause the degradation of the gain and the creation of bulk traps, degrading the timing resolution. One way to reduce the radiation induced degradation is to minimize the substrate thickness, thus improving the timing resolution of LGAD detectors.Two technology approaches have been contemplated: the use of SOI (Silicon on insulator) substrates and Silicon to Silicon bonding substrates, both with a very thin active silicon layer of 50μm. As a consequence, drifting distances of generated electrons and holes are significantly reduced, resulting in a decrease in the number of electrons and holes trapped by radiation induced bulk defects.A new family of thin detectors, produced in 2×2 arrays prototypes, for the ATLAS experiment High Granularity Timing Detector (HGTD) is proposed. These detectors are suitable for timing applications with time resolution in the range of 30 ps at 20 °C. Optimization of the LGAD structures for the HGTD experiment and the detector experimental performances are presented and discussed.

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (∼3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

Switching alternating current (AC) using a fully screen‐printed current‐driven transistor

The authors report on a large area, fully screen-printed transistors, using nanostructured silicon as the active material. The transistors are produced by simple screen printing processes under ambient conditions without the need for post-processing steps. The devices can be operated as two-way switches both with a direct or alternating current (AC). The authors demonstrated the operation of the devices printed on flexible substrates (office paper 80 g/m2) using silver as the conductive electrodes and highly doped p-type nanostructured silicon as the active layer. A method of switching sinusoidal AC using a single printed transistor is demonstrated at a frequency of 50 Hz at ambient condition. The silicon used as active materials, present domains, and blocks at a microscopic level, with an electric behaviour similar to one of the varistor-like components used as surge suppressors. So, unlike conventional transistors which rely on electric field modulation or charge injection, these AC switches operate by activation transport of charge carriers in the active silicon layer. Switching AC is achieved by applying a signal to the base which results in a change of the current's direction from between the collector and base to between the base and emitter.

Light trapping in thin film silicon solar cells via phase separated disordered nanopillars.

In this work, we have improved the absorption properties of thin film solar cells by introducing light trapping reflectors deposited onto self-assembled nanostructures. The latter consist of a disordered array of nanopillars and are fabricated by polymer blend lithography. Their broadband light scattering properties are exploited to enhance the photocurrent density of thin film devices, here based on hydrogenated amorphous silicon active layers. We demonstrate that these light scattering nanopillars yield a short-circuit current density increase of +33%rel with respect to equivalent solar cells processed on a planar reflector. Moreover, we experimentally show that they outperform randomly textured substrates that are commonly used for achieving efficient light trapping. Complementary optical simulations are conducted on an accurate 3D model to analyze the superior light harvesting properties of the nanopillar array and to derive general design rules. Our approach allows one to easily tune the morphology of the self-assembled nanostructures, is up-scalable and operated at room temperature, and is applicable to other photovoltaic technologies.

Improved Performance of Silicon Anodes Using Copper Nanoparticle Additive

Silicon continues to be an attractive anode material for use in lithium-based battery systems due to its high theoretical capacity and natural abundance. However, the widespread application of the silicon anode remains impeded due to notable, unfavorable characteristics observed during charge/discharge cycling. One such hindrance is the relatively poor electrical conductivity of silicon. Approaches to mitigating this issue often involve increasing the amount of conductive additive, but the additives are usually carbon-based or process-intensive. The focus of this research is the improvement of the electrical conductivity of the anode active layer by introducing nanoscale copper additive to the silicon structure. The fabrication of these anodes involved a simple, cost-effective procedure where the copper nanoparticle additive was homogeneously dispersed within the silicon active layer, and the anodes were tested using CR2032 type coin cells. The results of this research indicate excellent stability and improvements in the charge capacity of the cells with additive as a function of cycle testing. Surface characterization was performed using spectroscopy and imaging methods for comparison of anodes before and after charge/discharge cycling tests. SEM images show the successful integration of the copper nanoparticles within the silicon layer. Acknowledgement: This research was supported by the Office of Vice President for Research Innovation at the University of Nevada, Reno via an AIRE grant. Characterization of electrodes was conducted by Materials Characterization Nevada.