Silicidation Process Research Articles

Rapid Thermal Processing for Self-Aligned Silicide Technology

ABSTRACTA self-aligned titanium silicide process which combines the use of ion-beam mixing and rapid thermal processing (RTP) has been developed for CMOS VLSI applications. Shallow silicided junctions are formed by implanting dopants into silicide layers previously formed by ion-beam mixing with Si ions and low temperature annealing, and the subsequent drive-in of the implanted ions into the Si substrate during high temperature RTP. In addition, the formation of TiN on TiSi2 is achieved simultaneously during this process as a diffusion barrier for Al metallization. Short-channel MOS transistors with SALICIDE structure have been successfully fabricated and tested. Results of the impurity diffusion in silicide layer, the impurity segregation at both silicide/Si and oxide/silicide interfaces, contact stabilit of Al/TiN/TiSi2 structure, and device characteristics will be reported. Issues related to this process and its application to submicron device fabrication are discussed and foreseeable problem areas identified.

Shallow Junction Formation by the Redistribution of Species Implanted into Cobalt Silicide

Interest in CoSi2 as a metallization for very large scale integrated circuits (VLSI) has grown rapidly since the recent demonstration of a simple self-aligned process performed by rapid thermal annealing.1-4 Using a rapid thermal anneal (RTA) to directly silicide Co on Si yields smooth low-sheet-resistance films with little or no lateral diffusion and low contact resistance. In addition, it has been shown that rapid thermal annealing can result in reasonable quality epitaxial CoSi2 on (111) Si wafers.5 An important advantage of CoSi2 over the more commonly used TiSi2 metallization is the relative simplicity of its self-aligned silicidation process. Due to the low reactivity of Co with SiO2, a simple two-step self-alignment process is possible instead of the three-step process necessary with TiSi2.6 The primary disadvantage of CoSi2 is the amount of Si consumed for equal silicide sheet resistance. For example, to yield a silicide sheet resistance of 1.5 1/LD, Van den Hove 4 finds that compared to the TiSi, process, the CoSi, process would consume an additional 24 nm of Si. (This disadvantage can be minimized if very shallow junctions can be formed under the CoSi2.)

Nickel silicide formation by reaction of filament evaporated nickel with silicon substrate

Nickel silicide formation by reaction of tunsten filament evaporated nickel film with silicon substrate in flowing commercial nitrogen at temperatures in the range of 400 to 900°C has been investigated. The oxygen contained in the nickel film and in the nitrogen gas is found to greatly slow down/inhibit the silicidation process. The silicidation is found to restart only after removing the impurities chemically and subjecting the wafers once again to the annealing schedule as before. The sheet resistance is observed to decrease with increase of annealing temperature and time. This is attributed to the evolution of different silicide phases during annealing. The barrier height is found not to depend on silicide phases indicating that the reaction between silicon and nickel occurs during deposition at room temperature. A thin layer of SiO 2 is also observed to grow on top of nickel silicide. Various applications to VLSI are indicated.

Junction leakage in titanium self-aligned silicide devices

Successful utilization of a titanium self-aligned silicide (salicide) process for reproducible device fabrication with high yield requires junction leakage due to the silicide process to be minimized. The microstructure and microchemistry of titanium salicide shallow junction diodes were studied and correlated with junction leakage. The direct correlation between junction leakage and junction structure was established by using several analytical techniques. The main cause of large leakage current was found to be a loss of p+/n junction under the titanium silicide layer and formation of titanium silicide/n-silicon Schottky barrier contact at the perimeter of the diodes. Process parameters for low leakage titanium silicide/p+/n diode fabrication were also established.

Ion-beam-induced silicidation and its use in very-large-scale integration processing

The ion-beam-induced reaction of metal films on a silicon substrates is studied with emphasis on applications in very-large-scale integration processing. Using the Ti/Si system as an example it is shown that, in combination with subsequent rapid thermal annealing, silicides with excellent properties are formed in a uniform and reproducible way. When using dopant elements for the mixing, shallow junctions with a depth of the order of 0.1 μm are demonstrated, which show excellent electrical properties. The advantages of the ion-beam-induced metal-silicon reaction in a self-aligned silicide process are discussed.

Influence of P and As implantation of the formation of MoSi2

Molybdenum disilicide films have been formed by a reaction of Mo with polycrystalline silicon. Implantation of phosphorus or arsenic prior to reaction has been shown to have a large effect on the silicidation process. The object of implantation was to enhance the silicide reaction by creating damage at the metal-silicon interface. This, then, results in silicide films with less surface roughness (and a lower electrical resistivity). Molecular P+2 ions were found to be more effective in creating damage than single P+ ions, due to the fact that for P+2 ions two simultaneous collision cascades occur which overlap. Apart from the beneficial effect of implantation damage, the introduction of phosphorus has a deleterious effect on the properties of the silicide films. This phenomenon is explained by the presence of a thin and nonuniform native oxide layer which hinders the silicide reaction. Without addition of phosphorus, new nuclei for the silicide reaction can be formed due to stress introduced by the formation of the silicide, which will act upon the oxide and cause it to break up at some weak spot. The effect of phosphorus is proposed to be that it renders the oxide more viscous which prevents this process from taking place. The x-ray diffraction spectra revealed that the orientation of the grains in the polycrystalline MoSi2 films is influenced by the method of preparation.

Refractory metal silicides for self-aligned gate modulation doped n+-(Al,Ga)As/GaAs field-effect transistor integrated circuits

A refractory metal silicide process has been developed for the fabrication of self-aligned gate (Al,Ga)As/GaAs FET’s (MODFET’s). Completely planar, self-aligned gate by ion implantation MODFET’s have been fabricated and have demonstrated typical transconductances of 180–200 mS/mm at room temperature and over 300 mS/mm at 77 K. Self-aligned gate ring oscillator test circuits have demonstrated gate propagation delays as low as 17.6 ps/gate at 2.65 mW/gate at room temperature.

Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxide-semiconductor technologies

This paper reviews recent progress towards integrating the self-aligned titanium silicide process into VLSI NMOS and CMOS technologies, to simultaneously reduce the gate and junction sheet resistances to below 1 Ω/sq. In addition to reviewing the base line self-aligned TiSi2 process, the key issues that must be addressed if the process is going to be successfully integrated into a VLSI process flow, without having adverse effects on device parameters, will be discussed. Such issues are how the sheet resistance can be reduced to <1 Ω/sq without bridging between the gate and source/drain regions, the effect of silicide stress on gate oxide integrity, and how both P- and N-type junctions can be silicided without adversely affecting diode or transistor properties. Recent results on the hot electron hardness of silicided devices compared to unsilicided transistors will also be presented. The implementation of the self-aligned titanium silicide process using rapid thermal processing to simultaneously fabricate transistor gates and junctions with a sheet resistance of 1 Ω/sq will also be described. Using the self-aligned TiSi2 technology, fully functional VLSI CMOS and NMOS circuits of the 64K static random access memory class of complexity, with 1 μm gates, have been fabricated with yield that is similar to unsilicided parts.

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Effect of silicide process on bipolar transistor current gain

Emitter Gummel number of modern bipolar transistors is an important factor in determining device performance, especially for heavily doped, shallow junction transistors. Removal of even small amounts of the active dopant from the shallow emitter, e.g., Ar sputteretch and PtSi formation, can significantly reduce the current gain of bipolar transistors. A simple theory of bipolar transistor gain shows that degradation of current gain is due to the reduction of emitter Gummel number. Emphasis is placed on the control of the Ar sputteretch and PtSi formation to obtain desired current gain and to determine its implication in the development of advanced bipolar transistors with very shallow emitter junctions.

Effects of alumina substrate defects on thin-film interconnect patterns : R. C. Sundahl and E. J. Sedora. Proc. IEEE.59, No. 10 (1971), p. 1462

The Ni-based self-aligned silicide process has attracted a rapidly growing interest for contact metallization in Si technology, as the device dimensions are scaled down into the sub-100 nm regime. Incorporation of Ge in the electrodes of a MOSFET, i.e. gate and source/drain, in order to further enhance device performance, has made the study of Ni–Si1−xGex interactions a scientifically and technologically important issue. Among the different germanosilicides of Ni, NiSi1−uGeu (i.e. mono-germanosilicide, with u possibly different from x in the Si1−xGex) is the most desirable phase due to its low specific resistivity of 12–25 μΩcm. The focus of the present work is placed on issues concerning the phase and morphology stability of NiSi1−uGeu on single-crystal and polycrystalline Si1−xGex substrates. The related experimental data from our recent work are analysed with reference to two classics on the formation of silicides by d’Heurle [J. Mater. Res. 3 (1988) 167] and by d’Heurle and Gas [J. Mater. Res. 1 (1986) 205]. Influences of C and Pt on the stability of NiSi1−uGeu are also covered. The electrical properties of the NiSi1−uGeu–Si1−xGex contact are discussed referring to our latest experimental results.