Silicidation Process Research Articles

Prospects of silicide contacts for silicon quantum electronic devices

Metal contacts in semiconductor quantum electronic devices can offer advantages over doped contacts, primarily due to their reduced fabrication complexity and lower temperature requirements during processing. Some metals can also facilitate ambipolar device operation or form superconducting contacts. Furthermore, a sharp metal–semiconductor interface allows for contact placement in close proximity to the active device area avoiding damage caused by dopant implantation. However, in the case of gate-defined quantum dots in intrinsic silicon, the formation of a Schottky barrier at the silicon–metal interface can lead to large, nonlinear contact resistances at cryogenic temperatures. We investigate this issue by examining hole transport through metal oxide-semiconductor transistors with platinum silicide contacts on intrinsic silicon substrates. We extract the contact and channel resistances as a function of temperature and improve the cryogenic conductance of the device by more than an order of magnitude by implementing meander-shaped contacts. In addition, we observe signatures of enhanced transport through localized defect states, which we attribute to platinum clusters in the depletion region of the Schottky contacts that form during the silicidation process. These results showcase the prospects of silicide contacts in the context of cryogenic quantum devices and address associated challenges.

The feasibility of an ultrathin dual-barrier scheme to inhibit interfacial diffusion and reactions in contact stacks of Co/NiSi/Si

Self-assembled monolayers (SAMs) and self-forming barriers (SFBs) are highly effective barriers of copper (Cu) interconnect systems. However, the barrier capability of SAMs and SFBs to contact metallization of cobalt (Co), a new important interconnect material, is yet to be explored. Here, contact layers of NiSi are grown by a two-step silicidation process on Si. Then, an all-wet SAM-seeding and electroless-plating process is used to coat (in sequence) an amine SAM and a MnO-added (only 0.1%) Co film onto NiSi/Si, using a specifically formulated N2H4-CoSO4-MnSO4 bath. The thermal stability of the Co(MnO)/SAM/NiSi/Si is evaluated, using (unalloyed) Co/SAM/NiSi/Si as a control. The 1.3 nm-thin SAM cannot protect the Co/SAM/NiSi/Si from catastrophic failure upon annealing, associated with serious Co/Si interfacial diffusion and the formation of faceted CoSi crystallites and a layered Co2Si/CoSi2 nanostructures at specific locations. By contrast, the Co(MnO)/SAM/NiSi/Si maintains an intact stack after annealing. Collaborative research results generated from (scanning) transmission electron microscopy, nanoscratch testing and surface-energy measurements suggest that the thermal stability enhancement of the whole Co(MnO)/SAM/NiSi/Si contact stack is related to the interfacial segregation of the added MnO as sub-5-nm dispersive crystalline particles, giving multiple functionalities as a SFB, Co-grain strengthening agent, and wetting/adhesion promoter.

Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

A low-resistivity titanium silicide (TiSi2) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi2. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi2 by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi2. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 1014 cm−2. The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

Improved RFET Performance Using Dual-Aluminum-Contact (DAC)

The reconfigurable field effect transistors (RFET) enable the integration of MOS-type transistors (N-type and P-type) in a single device. The programming gate voltage (VPG) controls the transistor type [1]. A greater area efficiency in logic circuits can be obtained, due to the possible different logic operation, such as NAND to NOR in a single circuit [2 - 3]. Others application include the use of RFET in circuits for security reason in order to avoid the reverse engineering [4]. Figure 1 (A) and (B) show a special type of RFET called BESOI MOSFET that will be one of the devices used in this work.Many conventional RFETs contain NiSi source/drain (S/D) contacts, or other contacts with mid-gap S/D material, providing a symmetrical current between holes and electrons. However such contacts decrease injection of current [5 - 7]. Devices based on dual-doping (DD), provided a significant improvement in the current level, in addition to the ease fabrication due to the absence of the silicidation process, such technology cannot act in doping-free CMOS processes [6] [8]. Figure 2 shows the drain current as a function of the control gate voltage (IDS -VCG) for the BESOI MOSFET.This work presents a new proposal for a dual-contact S/D (DC) RFET, without the presence of DD regions and doping process, enabling dopants-free CMOS processes, using only S/D aluminum contacts, performed through Sentaurus TCAD simulations [9].Recently in the Integrable Systems Laboratory of the University of São Paulo (LSI-USP), two RFET with aluminum S/D contacts were reported. Both presented a high current for only one type of carrier (holes or electrons) [10 - 13]. The BESOI MOSFET conducts current through its back interface, where the channel between S/D contacts is formed by the bias of the programming gate (VPG), thus its operating mode is divided into P-type (VPG < 0 ) and N-type (VPG > 0). The transistor drain current is controlled by control gate voltage (VCG) [5] [10 - 11].The Figure 3 shows the drain current balanced as a function of the control gate voltage (ID -VCG), for aluminum BESOI MOSFET’s with and without annealing process (W/A, Wo/A) after the metal deposition [10 - 11]. Using both BE SOI MOSFET with S/D aluminum contact, without process doping, a new RFET Dual Aluminum Contact (DAC) is shown Figure 4.The challenge the design is to flow of current (holes) through the outer contact (W/A contact), due to the influence of the inner schottky low-barrier aluminum contact (Wo/A contact) near to the back interface. Figure 5 shows the carrier density as a function of the depth of the silicon under the inner contact, for different silicon thicknesses (tSi) and fixed programming gate voltage (VPG). The high concentration of electrons near to the inner contact, provided an ohmic contact for electrons [11], however near the back interface, an increasing concentration of holes, due to VPG. Increasing the tSi reduces the influence of charges near the back interface, for tSi=30nm the current flow between the outer contact is possible. However, increasing the tSi decreases the efficiency of the control gate, added to the high electric field in back interface increases IOFF (similar effect described for FD SOI [14]). The Figure 6 shows the drain current as a function of the control gate voltage of BESOI nMOSFET with tSi = 30nm. Such effect can be mitigated, optimizing the coupling the gates. Figure 7 shows the final proposal of the BESOI MOSFET DAC.Figure 8 shows the IDS-VCG for different thicknesses in the S/D contacts (tsi cont). As shown in Figure 5, a greater thickness in the contacts makes possible a smaller influence of the inner contact near the back interface, allowing greater concentrations of gaps, so consequently there is an increase in the p-mode current. However, increasing the thickness of the contacts promotes a reduction in the electron current, due to the increase in the series resistance in inner contact in n-mode.Figure 9 presents the ID-VCG for different VPG bias for the DAC BESOI MOSFET (A) and NiSi BESOI MOSFET (B). Using the DAC BESOI MOSFET, an increase in current was obtained in relation to the NiSi contact (900% in n-type and 300% in p-type), without the addition of doping regions (dual-doping) and using a single contact metal (Aluminum). Figure 1

Improved performance of FDSOI FETs at cryogenic temperatures by optimizing ion implantation into silicide

Band tailing is a critical issue for cryogenic CMOS, which significantly degrades the performance of conventional MOSFETs at cryogenic temperature. The band tail arises primarily due to Gaussian-distributed localized states, which can be induced by ion implantation during source/drain formation. In this study, we investigate the impact of various ion implantation schemes on the subthreshold behavior of cryogenic fully depleted (FD) SOI MOSFETs. By optimizing the ion implantation into silicide (IIS) process, we were able to reduce the density of localized states and achieve a steep switching performance at 5 K. We systematically examine the effects of ion implantation angle and activation temperature of IIS on the device performance at cryogenic temperatures.

Si0.5Ge0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

In this paper, the Si0.5Ge0.5 channel FinFET preparation on an in situ doped SiGe strain relaxed buffer (SRB) and its electrical characteristic optimization were explored in detail. First, an in situ phosphorus doped three-layer SiGe SRB is developed and a perfect Si0.5Ge0.5/Si0.7Ge0.3 SRB fin profile is achieved under the conventional STI last scheme. Then, the Si0.5Ge0.5 channel FinFET is successfully prepared according to the standard integration process of Si channel FinFET. However, it suffers bad electrical performance due to poor Si0.5Ge0.5 channel interfacial property and high S/D series resistance. Therefore, a channel passivation process including an in situ ozone oxidation combined with HfO2/Al2O3 bi-layer gate dielectric, and a S/D silicide process are simultaneously introduced to optimize its electrical characteristics. As a result, its SS can be decreased from 174 to 104 mV/dec, and its driven current under |VGS| = |VDS| = 0.8 V can be increased from 12 to 314 μA/μm. Therefore, these newly developed technologies are practical for the Si0.5Ge0.5 channel FinFET.

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> at 5.5 K.

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process.

In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0.3/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si0.7Ge0.3/Si fin is attained by further optimizing the etching process under the HBr/He/O2 plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si0.7Ge0.3 channel. As a result, the selectivity of Si to Si0.7Ge0.3 can reach 32.84 with a signature of “rectangular” Si0.7Ge0.3 extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si0.7Ge0.3 nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, Ion/Ioff ratio of 9 × 105 and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under VDS = VGS = −0.8 V due to its large resistance of source and drain (9.2 × 105 Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 104 Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and Ion/Ioff ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.

Controlled Silicidation of Silicon Nanowires Using Flash Lamp Annealing.

Among other new device concepts, nickel silicide (NiSix)-based Schottky barrier nanowire transistors are projected to supplement down-scaling of the complementary metal-oxide semiconductor (CMOS) technology as its physical limits are reached. Control over the NiSix phase and its intrusions into the nanowire is essential for superior performance and down-scaling of these devices. Several works have shown control over the phase, but control over the intrusion lengths has remained a challenge. To overcome this, we report a novel millisecond-range flash lamp annealing (FLA)-based silicidation process. Nanowires are fabricated on silicon-on-insulator substrates using a top-down approach. Subsequently, Ni silicidation experiments are carried out using FLA. It is demonstrated that this silicidation process gives unprecedented control over the silicide intrusions. Scanning electron microscopy and high-resolution transmission electron microscopy are performed for structural characterization of the silicide. FLA temperatures are estimated with the help of simulations.

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS) field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs, which were formed with the process compatible in the main stream industry. The VSAFETs with self-aligned high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gates (HKMGs) were fabricated with epitaxy of Si/SiGe/Si sandwich structure, an isotropic quasi-atomic-layer-etch (qALE) process, and gate replacement process. The gate-length of VSAFETs is mainly determined by the thickness of SiGe film grown by epitaxy. The NW diameter and NS thickness could be obtained by the isotropic qALE method, which can be used to the Si-selective etching of SiGe. As a result, p-type NS and NW VSAFETs with good device characteristics were fabricated. Device performance and the influence of silicide, Ge fraction, Si cap, and high thermal process were investigated; threshold voltage tuning and reliability were also discussed.

Improvement of Resistive Switching Characteristics of Titanium Oxide Based Nanowedge RRAM Through Nickel Silicidation

Low operation power and high endurance of resistive random access memory (RRAM) as a synaptic device are critical parameters for in-memory computing applications. Yet, high power consumption and reliability issue of silicon bottom electrode (BE) RRAM hinder its commercialization as a synaptic device. In this experiment, we report on the improvement of switching characteristics of silicon BE nanowedge RRAM via the Nickel (Ni) silicidation process. Existing highly doped Si-BE forms a SiO2 interfacial layer (IL) during a switching layer deposition and increases an effective thickness, leading to increased voltage drop within the RRAM device and large cycle-to-cycle variations. By siliciding the Si-BE with Ni, the issue of IL formation is removed and the resistance of metallic NiSi BE is further reduced compared to Arsenic (As <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ) doped Si BE. Both dc and ac analyses of the fabricated NiSi-BE nanowedge RRAM have shown the reduction of overshoot and switching current down to 55% of the original value. Transmission electron microscopy (TEM) and energy-dispersive spectroscopy (EDS) analysis convinced the formation of NiSi BE. In addition, gradual switching characteristics, uniform low resistance state (LRS), and better endurance of NiSi-BE nanowedge RRAM enable the Si compatible approach to fabricate a large-size RRAM cross-point array for utilization in hardware-implemented neuromorphic computing applications.

Thermal Silicidation of Ni/SiGe and Characterization of Resulting Silicide Films Using Raman Spectroscopy and X-ray Diffraction

For advanced application specific devices, combinations of Si/Ge, Ge/Si, Si1-xGex/Si are frequently introduced in the device fabrication process. Epitaxy, condensation and annealing processes are commonly used for controlling the Ge content to a desired level. Strain and crystallinity can be affected by a small variation in composition or Ge content, which can result in device performance deterioration or failure. Thus, the composition, strain and crystallinity must be carefully monitored and controlled throughout the manufacturing process. The electrode formation process is also very critical for successful device fabrication. Any spikes and/or electrically active defects near junctions can be fatal to the device yield. Silicidation processes and resulting silicides must be investigated as much as possible using various non-invasive material characterization techniques.In this study, we report the thermal silicidation characteristics of Ni/Si1-xGex with various Ge content under different annealing temperatures in the range of 225oC ~ 400oC in N2 ambient. Thermal silicidation was performed in a stacked hotplate-based SAO-302LP system designed for 300mm wafers. For resulting silicide characterization, measurements of sheet resistance, Raman spectra, X-ray diffraction curves as well as scanning electron microscopy (SEM) observations were performed. We have studied Ge content and annealing temperature dependence on the resulting electrical and crystallographic silicide characteristics.Figure 1 shows 647nm excited Raman spectra and X-ray diffraction (XRD) curves from reference Si, and resulting silicide from Ni/Si0.75Ge0.25 before and after annealing under at 235oC, 310oC and 400oC.Raman spectra and sheet resistance measurements showed silicide formation and silicide layer thickening with increasing annealing temperature. XRD curves clearly indicated the change of crystalline phase of resulting silicide with annealing temperature increase. Various aspects of thermal silicidation and its characterization will be discussed at the conference. Figure 1

Thermal Silicidation of Ni/SiGe and Characterization of Resulting Nickel Germanosilicides

Thermal silicidation characteristics of Ni/Si1-xGex with various Ge content was studied under different annealing temperatures in the range of 225 °C ∼ 400 °C in 100% N2 ambient. TiN capped Ni/Si1-xGex/Si/SiO2/Si wafers with x values in the range of 0.15 and 0.30 in 0.05 intervals were used. Thermal silicide formation was performed in a stacked hotplate-based annealing system designed for industrial 300 mm wafer fabs. For silicide characterization, measurements of spectral reflectance, sheet resistance, Raman spectra as well as X-ray diffraction curves were performed to investigate changes of optical properties, electrical properties, crystallographic phases during silicide formation. Effects of Ge content and annealing temperature on the electrical and crystallographic properties of the resulting thermal silicides (nickel germanosilicides) were investigated. Reaction mechanisms were discussed based on the characterization results. Multiwavelingth micro-Raman spectroscopy was found to be very promising as a non-contact, in-line silicidation process monitoring technique. For production worthiness verification of the thermal silicidation process, temperature sensitivity curves of sheet resistance, its uniformity and detailed sheet resistance maps were investigated using 8 nm thick Ni films on 300 mm diameter, epitaxial Si0.8Ge0.2/p−-Si wafers without a capping layer. Manufacturability of Ni/Si0.80Ge0.20/Si wafers were also verified using a stacked hotplate-based, nearly isothermal, annealing system.

(Invited) Nickel and Nickel-Platinum Silicide for BiCMOS Devices

Recently, the world’s fastest SiGe-HBT was presented by IHP researchers [1], which applies low ohmic nickel silicide (NiSi). Among other measures, this feature contributed to speed improvements. On the other hand, the integration of low-ohmic NiSi creates the risk for NiSi defects which could result in increased MOSFET leakage currents. The goal of this contribution is to find out from several two-step silicidations of Ni or NiPt layers a suitable process for a BiCMOS technology which enables low silicide RS for high cutoff frequencies of bipolar and MOS transistors without degradation of leakage currents. In result, a 300°C/450°C silicidation is proposed providing RS values of 3 to 4 Ω for both NiSi and NiPtSi. However, only the NiPtSi shows acceptable low leakage currents compared to NiSi. Therefore, NiPt extends the silicide process window for HBTs and MOSFETs.The phase transitions of Ni and NiPt silicides as a function of temperature are shown in Fig. 1, where the temperature range of the targeted NiSi phase is enlarged for NiPt compared to Ni. The investigated two-step NiSi formations are listed in Table 1. The NiPt layers were deposited in an Applied Materials laboratory. First, Ni2Si was formed by furnace anneal, low pressure anneals, or by a NiPt sputtering at 400°C. The Ni rich silicide was converted into NiSi by a second anneal at 450°C.The final Ni(Pt)Si sheet resistance (RS Ni(Pt)Si:1.+2.Ann) was tunable from 1.5 Ω to 10.5 Ω by the temperature and time of the first anneal (Fig. 2). At 300°C, the RS saturates at 3.3 Ω for 20 nm Ni and 1.6 Ω for 40 nm Ni, respectively. This indicates full Ni consumption. The furnace anneals at 200°C and 230°C do not show any RS saturation since Ni is consumed only partially. An RS increase for NiSi and NiPtSi on PSD (p source-drain) compared to NiSi on substrate is observed.One figure of merit of SiGe-HBTs is the maximum oscillation frequency fmax, which depends by the following equation fmax=sqrt(fT/(8πrBcBC)) on the transit frequency fT, the base resistance rB, and the collector-base capacitance cBC. A silicide resistance variation could mainly influence rB. In Fig. 3a, the sheet resistance of the silicided base polysilicon (RS BasePolySilicide) together with fmax of two HBT layouts are plotted for several silicide formations. It exists a correlation between fmax and RS BasePolySilicide, which is shown in Fig. 3b. In general, fmax could be enlarged by a silicide resistance reduction for special HBT layouts.For these low-ohmic and thick Ni(Pt)Si layers, special attention has to be paid to the MOSFET leakage currents, which can be enlarged by lateral silicide pipes towards the conducting channel or by defects along the SD – STI (shallow trench isolation) interface [2]. Another leakage current source are silicide spikes shortening in a perpendicular direction the SD and the well. Three types of P+Nwell and N+Pwell diodes are suitable to determine and distinguish these silicide based yield killers: area diodes to detect spikes, STI separated island diodes to recognize SD-STI defects, and diodes with long poly-gates on SD-well areas to determine pipes at gate edges. In result, the area and island diodes showed no leakage current increase for the studied silicidations, i.e. defects along the SD-STI edge and spikes are not critical here. The leakage currents of gate-edged diodes on N+Pwell and P+Nwell are presented in Fig.4. Both diode types show low leakage currents for the 200°C and 230°C anneals, because the low lateral silicidation at these temperatures reduces the probability for piping. At 300° the N+Pwell leakage current increases slightly up to 2x10-9A, but significantly up to 1x10-7A for the P+Nwell diode. This is a clear indication for pipes at the gate edges [3]. In contrast, almost no enhanced leakage current was observed for the NiPt silicidations with 200° to 300°C anneals. The pipe suppression of the NiPt silicide system might be caused by the Pt agglomeration at the silicide-SD interface [4]. The limits of the NiPt pipe suppression are shown for N+Pwell diodes silicidated with a NiPt deposition at 400°C. Leakage currents of 1x10-8A could indicate NMOS-typical pipes, as described by Yamaguchi [5].In summary, silicide layers with low RS values of 3Ω to 4Ω were formed by two-step annealing of Ni and NiPt at 300°C and 450°C. These silicides support high fmax values of SiGe HBTs. However, only the NiPt silicide process provided acceptable low leakage currents of MOSFET test structures indicating an extended process capability of NiPtSi compared to NiSi. Figure 1

Thermal Silicidation of Ni/SiGe and Characterization of Resulting Silicide Films Using Raman Spectroscopy and X-ray Diffraction

Thermal silicidation characteristics of Ni/Si1-xGex with various Ge content was studied under different annealing temperatures in the range of 225oC ~ 400oC in N2 ambient. TiN capped Ni/Si1-xGex/Si/SiO2/Si wafers with x values in the range of 0.15 and 0.30 in 0.05 intervals were used. Thermal silicide formation was performed in a stacked hotplate-based annealing system designed for 300mm wafers. For silicide characterization, measurements of spectral reflectance, sheet resistance, Raman spectra as well as X-ray diffraction curves were performed to investigate optical properties, electrical properties, crystallographic phases and reaction mechanisms. Multiwavelingth micro-Raman spectroscopy was found to be very promising as a non-contact, in-line silicidation process monitoring technique. We have studied effects of Ge content and annealing temperature dependence on the electrical and crystallographic properties of the resulting thermal silicides (nickel germanosilicides).

Efficient Atomic-Resolution Uncertainty Estimation for Neural Network Potentials Using a Replica Ensemble.

Neural network potentials (NNPs) are gaining much attention as they enable fast molecular dynamics (MD) simulations for a wide range of systems while maintaining the accuracy of density functional theory calculations. Since NNP is constructed by machine learning on training data, its prediction uncertainty increases drastically as atomic environments deviate from training points. Therefore, it is essential to monitor the uncertainty level during MD simulations to judge the soundness of the results. In this work, we propose an uncertainty estimator based on the replica ensemble in which NNPs are trained over atomic energies of a reference NNP that drives MD simulations. The replica ensemble is trained quickly, and its standard deviation provides atomic-resolution uncertainties. We apply this method to a highly reactive silicidation process of Si(001) overlaid with Ni thin films and confirm that the replica ensemble can spatially and temporally trace simulation errors at atomic resolution, which in turn guides the augmentation of the training set. The refined NNP completes a 3.6 ns simulation without any noticeable problems. By suggesting an efficient and atomic-resolution uncertainty indicator, this work will contribute to achieving reliable MD simulations by NNPs.

A Low-Temperature Nickel Silicide Process for Wafer Bonding and High-Density Interconnects

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal-silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion.

Enhanced thermoelectric properties of cobalt silicide-silicon heterostructured nanowires

Silicon nanowires (SiNWs) have attracted attention as promising high efficiency thermoelectric materials by significantly improving the thermoelectric efficiency of silicon. Here, we have fabricated cobalt silicide/silicon heterostructure on both ends of nanowires using self-aligned silicide (salicide) process. By forming cobalt silicide (CoSi2) layer on SiNWs, the thermal conductivity of SiNWs with diameters of 200, 350, and 500 nm decrease to 25.1, 31.3, and 38.1 W·m−1·K−1, respectively, which is about 8% reduction on average. Since the phonon nanoinclusion scattering is influenced by the density of the nanoinclusions, the thermal conductivity tends to decrease as the volume fraction of CoSi2 in SiNWs increases. The Seebeck coefficient of the heterostructured nanowires increases to 255 μV/K, which is mainly attributed to the low-energy charge carrier filtering effect due to the Schottky barrier at the CoSi2/Si interfaces. The measurements show that the figure-of-merit ZT of the heterostructured nanowires is improved by 10% on average compared with the conventional SiNWs. Consequently, the CoSi2/Si heterostructured nanowires enhance the thermoelectric properties of SiNWs effectively by suppressing phonon transport and improving electron flow.

In Situ Transmission Electron Microscopy Analysis of Copper-Germanium Nanowire Solid-State Reaction.

A promising approach of making high quality contacts on semiconductors is a silicidation (for silicon) or germanidation (for germanium) annealing process, where the metal enters the semiconductor and creates a low resistance intermetallic phase. In a nanowire, this process allows one to fabricate axial heterostructures with dimensions depending only on the control and understanding of the thermally induced solid-state reaction. In this work, we present the first observation of both germanium and copper diffusion in opposite directions during the solid-state reaction of Cu contacts on Ge nanowires using in situ Joule heating in a transmission electron microscope. The in situ observations allow us to follow the reaction in real time with nanometer spatial resolution. We follow the advancement of the reaction interface over time, which gives precious information on the kinetics of this reaction. We combine the kinetic study with ex situ characterization using model-based energy dispersive X-ray spectroscopy (EDX) indicating that both Ge and Cu diffuse at the surface of the created Cu3Ge segment and the reaction rate is limited by Ge surface diffusion at temperatures between 360 and 600 °C. During the reaction, germanide crystals typically protrude from the reacted NW part. However, their formation can be avoided using a shell around the initial Ge NW. Ha direct Joule heating experiments show slower reaction speeds indicating that the reaction can be initiated at lower temperatures. Moreover, they allow combining electrical measurements and heating in a single contacting scheme, rendering the Cu-Ge NW system promising for applications where very abrupt contacts and a perfectly controlled size of the semiconducting region is required. Clearly, in situ TEM is a powerful technique to better understand the reaction kinetics and mechanism of metal-semiconductor phase formation.

Optimal Nitrogen Incorporation in Nickel Silicide for Thermally Stable Contact Formation.

Nickel silicide (NiSi) is commonly used as a contact material for metal junctions but the poor thermal instability of NiSi above 600 °C has limited the further scaling down of devices and the implementation of novel schemes, such as monolithic 3-dimensional integration. This paper suggests a process to improve the thermal stability of NiSi through nitrogen incorporation during the silicidation process. The optimal level of nitrogen incorporation in NiSi reduced the nickel diffusion rate and enhanced the thermal stability by preventing the formation of a nickel disilicide phase. On the other hand, a higher level of N incorporation led to Ni3N formation, which impeded the complete transformation to NiSi. Therefore, it is essential to incorporate the optimal content of N. In this study, NiSi with 3.9% N incorporation showed superior electrical characteristics, such as the sheet resistance, junction leakage, and stable Schottky barrier height, even after high-temperature post silicidation annealing at 600 °C for 30 min.