Abstract
In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0.3/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si0.7Ge0.3/Si fin is attained by further optimizing the etching process under the HBr/He/O2 plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si0.7Ge0.3 channel. As a result, the selectivity of Si to Si0.7Ge0.3 can reach 32.84 with a signature of “rectangular” Si0.7Ge0.3 extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si0.7Ge0.3 nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, Ion/Ioff ratio of 9 × 105 and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under VDS = VGS = −0.8 V due to its large resistance of source and drain (9.2 × 105 Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 104 Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and Ion/Ioff ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.
Highlights
The vertically stacked horizontal gate-all-around (GAA) transistors are established as the most promising candidate to the FinFETs in sub-5nm technology node, due to the excellent electrostatic and short channel control [1–3]
SiGe materials, especially those with Ge concentration between 20% and 40%, have been considered as the channel material of GAA devices. This is because they have higher electron and hole mobility, better negative bias temperature instability (NBTI) reliability [8,9] than Si and are more compatible with present Si platform [9–11]
The stacked Si0.7 Ge0.3 NWs were subsequently released in the replacement metal gate (RMG) module by using an optimized ACT@SG-201 solution for the selective removal of Si sacrificial layers
Summary
The vertically stacked horizontal gate-all-around (GAA) transistors are established as the most promising candidate to the FinFETs in sub-5nm technology node, due to the excellent electrostatic and short channel control [1–3]. SiGe materials, especially those with Ge concentration between 20% and 40%, have been considered as the channel material of GAA devices. This is because they have higher electron and hole mobility, better negative bias temperature instability (NBTI) reliability [8,9] than Si and are more compatible with present Si platform [9–11]. The fabrication of stacked SiGe nanowire/nanosheet (NW/NS) GAA devices still face many challenges, such as a high-quality stacked SiGe/Si fin structure preparation, high selectively SiGe NW/NS release, inner spacer, source/drain (S/D) epitaxial process, etc. These processes are critical for the preparation of Nanomaterials 2022, 12, 889.
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