Signal Integrity Simulation Research Articles

Enhanced Cu-Cu bonding for ultrahigh-density interconnection: Co passivation bonding with non-oxidation interfaces

Cu-based hybrid bonding, known for its high density and low latency, is widely applied in big data throughput scenarios. However, Cu joints are prone to oxidation and perform poorly at fine pitches, hindering signal transmission and leading to failures in integrated devices. One of the most promising approaches to overcome these challenges is applying a cobalt (Co) passivation layer on the Cu surface owing to its preferable electrical and anti-electromigration behavior in sub-micron scale. However, the high melting point (∼1500 °C) and inevitable oxidation of the Co film coated on Cu are scarcely evitable. In this work, a ternary plasma composed of Ar, NH3, and H2O is introduced to activate the surface of the Co-passivated Cu, facilitating bonding at a temperature of 200 °C. Significant surface and interface electrical resistivity reductions were observed, reduced to 67.5 % and less than 10 %, respectively. Additionally, tensile strength more than doubled with ternary plasma activation attributed to the continuous and tightly bonded Co-Co interface. The application of this Co-passivated Cu bonding structure is evaluated through signal integrity simulations for 3D interconnection with ultrafine pitch. In summary, this work provides guidelines for the future fabrication of high-performance interconnection structures.

A practical ball‐grid‐array transition modelling methodology for accurate and fast multi‐interposer package simulation

AbstractAn equivalent circuit modelling methodology for the ball‐grid‐array (BGA) transition is proposed and validated with full‐wave electromagnetic simulation and measurement results. The BGA transitions modelled with the proposed methodology are validated to have a good accuracy up to 40 GHz. Unlike the existing BGA modelling methodologies which cannot model the BGA transition with short transmission lines within the anti‐pad region, the proposed methodology is developed from the practical BGA modelling scenario and models the irregular‐shape solder pads with transmission lines within the anti‐pad region. The BGA transitions modelled with the proposed methodology can be used for accurate and fast signal integrity simulations, analyses, and optimizations on 2.5D and 3D packaging. Additionally, factors impacting the accuracy of the equivalent circuit model are revealed by the proposed methodology.

White Rabbit Expansion Board: Design, Architecture, and Signal Integrity Simulations

The White Rabbit protocol allows synchronization and communication via an optical link in an integrated, modular, and scalable manner. It provides a solution to those applications that have very demanding requirements in terms of synchronization. Field-programmable gate arrays are used to implement the protocol; additionally, special hardware is needed to provide the necessary clock signals used by the dual-mixer time difference for precise phase measurement. In the present work, an expansion board that allows for White Rabbit functionality is presented. The expansion board contains the oscillators required by the White Rabbit protocol, one running at 125 MHz and another at 124.922 MHZ. The architecture of this board includes two oscillator systems for tests and comparison. One is based on VCOs and another on crystal oscillators running at the desired frequencies. In addition, it incorporates a temperature sensor, from where the medium access control address is extracted, an electrically erasable programmable read-only memory, a pulse-per-second output, and a USB UART to access the White Rabbit IP core at the field-programmable gate array. Finally, to ensure the quality of the layout design and guarantee the level of synchronization desired, the results of the power and signal integrity simulations are also presented.

Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages

This work presents an improved input–output (IO) buffer model for signal and power integrity simulation, including power/ground supply voltage (PGSV) variations for the buffer’s input and output stages. Both stages are mathematically modeled from a formulation that is derived from nonlinear electrical circuit analysis, an important aspect that grants these models a good level of generality and, simultaneously, high accuracy. The proposed IO buffer model is linear in the parameters and, therefore, extractable through the linear least-squares technique from the signals acquired in an IO buffer characterization setup. Several validation scenarios, supported on two CMOS driver’s transistor technologies, are performed to evaluate the accuracy of the proposed model. In addition, a comparative analysis is provided, confronting the proposed model’s performance against that of the input/output buffer information specification (IBIS) model, evidencing an outstanding modeling improvement provided by the proposed model.

IBIS MODEL ACCURACY IMPROVEMENT USING VARIABLE STEP

In all times of integrated circuits (IC) manufacturing, the speed of getting the product on the market has been the main problem for all manufacturers. The main reason for late products has always been the speed of the tools that carry out the testing. The main simulator used by every manufacturer is the SPICE simulator, but with the SPICE simulator it can take up to months to simulate the whole TXRX macro. But since the 1990s with the introduction of the I/O Buffer Information Specification (IBIS) models, the testing time has decreased dramatically. A method is proposed to generate IBIS models with a variable step, that will help to increase the accuracy of the IBIS model during signal integrity (SI) simulations and will correlate with SPICE simulations better. The proposed method can be implemented for all types of TX drivers and IBIS models.

Analysis of Pre-Driver and Last-Stage Power-Ground-Induced Jitter at Different PVT Corners.

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct DC supply voltages at the pre-driver (i.e., /) and last stage (i.e., ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

Development and Implementation of a Low-Cost Test Solution for High-Precision ADC Chips Based on Intelligent Sensor Networks

Analog-to-digital converters (ADCs) are moving toward high speed and high resolution for low-cost testing. Based on the theory of intelligent sensor network, this paper designs a low-cost test solution for high-precision ADC chips, which solves the problems related to signal integrity. It mainly includes the following: designing an appropriate circuit connection scheme, planning an appropriate PCB stack-up structure, formulating detailed layout and wiring constraints, etc., and building a high-speed ADC test platform to obtain static and dynamic performance; based on the existing instruments in the laboratory, the effects of different signal sources, different input powers, and the presence or absence of filters on the dynamic performance of high-speed ADCs are studied. In the simulation process, the HyperLynx simulation platform is used to design and simulate the signal integrity of the high-speed acquisition board. Combined with the relevant theoretical knowledge of the signal integrity of high-speed digital circuits, the signal integrity analysis and simulation of the ADC module circuit and the DDR3 high-speed memory circuit are carried out, respectively. The results show that, taking the histogram method as a reference, when the optimal 30 windows are selected, the integral nonlinearity (INL) error of the proposed method is 0.12 LSB, the highest sampling frequency is up to 5GSps, and 61440 sampling points are required. The time is reduced by about 30% compared with the excitation error identification and removal (SEIR) method, which effectively improves the low-cost test effect of the ADC chip.

Fast Multiple Edge Response Method Based on the Design of Experiment and Machine Learning

The multiple edge response (MER) method can accurately capture the nonlinear characteristics in signal integrity simulations. However, transient simulation is time-consuming to obtain all the edge responses for high-order MER. A fast method based on the design of experiment (DoE) and machine learning is proposed in this letter to obtain all the edge responses for a severe nonlinear link. The DoE is used to generate a few training sets for an artificial neural network (ANN). The ANN uses the generated training sets to build a precise model. The developed ANN model predicts the remaining edge responses. The proposed method takes 9.8 min to obtain all the responses, which is 92 min for transient simulations for the ninth-order MER. The results show that the eye height and width error between the proposed method and measurement is less than 5%.

S-Parameter Sampling in the Frequency Domain and its Time-Domain Response

S-parameter characterization of high-speed interconnect components is prone to numerical, modeling, and/or measurement error due, in part, to the sampled nature of the data. This is a problem in modern package design where extensive signal integrity simulations are required to validate a system's performance. This article presents a new method of treating sampled S-parameter data where a criterion is developed to clearly state the minimum number of S-parameter frequency points required to adequately represent an analog physical system in the frequency domain. This criterion is akin to the Nyquist principle when sampling in the time domain. Based on this principle, the proper time-domain representation of S-parameters can be obtained using the inverse fast Fourier transform (IFFT). However, in order to use the IFFT, the bilinear transformation is applied to the vector fit S-parameters to place them in the z-domain. From the z-domain, the proper discrete impulse response is obtained. A lower bound, based on the discrete Heisenberg principle, is also offered to deal with frequency-time resolution of the S-parameters. The proposed method is successfully tested in the measured and simulated S-parameter data. The usefulness of this method is to accurately represent the time-domain behavior of the physical system S-parameter data, i.e., time delay causality, and, therefore, facilitates the applications of well-developed digital signal processing (DSP) techniques in S-parameter sampled data.

Parallel, Optimized, Error Maxima-Agnostic, Pole Residue Equivalent System Solver

Fitting of sampled frequency response data to a rational function is often required for macromodeling of advanced microelectronic packages. The pole residue equivalent system solver (PRESS) method was recently proposed, as a novel fitting method that builds the global fit from local fits, computed from at most three data points at an error peak. To increase the fitting accuracy of PRESS, the error-maxima agnostic PRESS (EMPRESS) was proposed, but it is computationally intensive as the central processing unit needs to sequentially perform the local fits at all the frequency sample points before choosing the best among them. In this paper, we propose the parallel optimized EMPRESS (POEMPRESS) to reduce the computational complexity of EMPRESS while improving the fitting performance. POEMPRESS optimizes both the EMPRESS algorithm and its implementation through: 1) simplified local fit types, enabling the algorithm to rely on at most two data points only, and 2) an algorithm that can be implemented on graphics processing units for rapid parallel computation and evaluation of local fits at all the frequency points. The proposed algorithm is demonstrated on the interconnects of a microelectronic package. The results show that POEMPRESS is effective in fast macromodeling of complex interconnects for signal and power integrity simulations.

Design of high density SiP for complex computing system in micro SD format

This paper addresses the design process for the miniaturization of a complex computing system within the micro SD format. The complete device is capable of running a Linux OS in a standalone mode. The process is illustrated by a real design example that has been taken through all the steps from architecture through a PCB hardware prototype to a fully integrated miniature SIP solution. The design process starts with a detailed architecture definition describing in detail the individual functions that must be implemented within the design. Once the architecture has been defined a detailed schematic is created, in which care is taken to ensure that all the components will be available in die format or low profile WLCSP so as to fit the low profile of the micro SD card. Prior to starting detail design of the SiP a complete working prototype must be constructed using packaged parts mounted on a PCB. This step ensures that the complete system is functional and any firmware, OS development or software can be tested independently of the SiP. This breadboard also allows for experimentation on passive BoM reduction, a necessary step towards reducing component count prior to SiP integration. A revised schematic for the SiP is created in which the packaged components are replaced by bare die equivalents with all the individual bond pads. Prior to this step negotiations have to be made with all bare die suppliers to confirm availability and obtain detailed information concerning the die pad layout and technology. Appropriate substrate technology choice has to be made. Miniaturization of complex heterogeneous SiPs requires best in world class substrates. In this case extremely high definition 6-layer build up substrates were required with complex plating techniques for wire-bonding compatibility. The detailed design is carried out using standard PCB or SIP layout tools. In the design example a total of 6 dies, 4 packaged parts and 40 small chip SMTs were integrated. A memory stack of 3 dies plus the 6 layer substrate and over-mold was integrated within the maximum height of 0.8mm. This required the use of state of the art Film on Wire with dies thinned to less than 80im. Signal integrity simulations of the substrate are made at this stage for critical parts of the system. The debug process of such complex designs requires constant interaction between breadboard performance and SIP performance to determine root causes for potential failure of the SiP. Since the design has 1000 nets of which only 35 are visible on the SIP, probing is impossible. In the actual design example the miniature micro SD SiP is fully functional and operates as a stand-alone Linux computer.

Enhanced Mpilog macromodels for Signal and Power Integrity Simulations

Due to increasingly stringent low-cost and small form-factor design constraints, Signal and Power Integrity analyses (SI&PI) have gained a paramount importance in the definition and optimization of mobile platforms. Operating margins are dramatically reduced in order to meet all the required design targets and constraints (extensive re-use, time-to-market, etc.). In this scenario, transistor-level simulations for platform-level analyses are inefficient and often, impractical. I/O-buffer models become essential and their accuracy is crucial for the reliability of SI&PI studies. As data-rates increase, signaling swing reduces and power-supply voltage noise becomes inevitable, state-of-the-art legacy models are limited for SI&PI co-simulations. This work summarizes the recent enhancements of “Mpilog”-class macromodels for high-speed I/O-buffers. Mpilog macromodels reproduce voltage and currents at I/O and (multiple) supply ports as weighted combinations of pull-up/pull-down static and dynamic components. The static parts are extracted via nested DC sweeps simulations and reproduced by tensor representations obtained via high-order singular value decomposition (SVD) processes. The dynamic components are described by linear state-space models identified from device's transient responses to suitable stimuli. For transmitters, the weighting functions match the output-port transitions and the dynamic supply-current profiles, capturing also the dependency of switching delays upon supply-voltage fluctuations; this is a key feature that enables Mpilog macromodels to precisely reproduce simultaneous-switching-noise (SSN) effects in complex system-level SI&PI simulations. The macromodels can be readily synthesized as SPICE netlists (including resistors, capacitors and controlled-sources) or Verilog-A codes; this allows their use in any SPICE-type electrical solver. Several examples of realistic SI&PI simulations for single-ended and differential interfaces are presented. Transistor-level simulations are compared with the corresponding ones based on Mpilog-macromodels: the resulting accuracy and the speed-up factors are extensively discussed. Comparisons with state-of-the-art legacy models (IBIS) are also discussed.

Method of Effective Roughness Dielectric in a PCB: Measurement and Full-Wave Simulation Verification

Surface roughness topography of printed circuit boards (PCBs) needs to be included in signal integrity simulations in order to accurately predict the insertion loss of the structure and its delay time. An effective roughness dielectric (ERD) model can be used to substitute an inhomogeneous interface between copper foil and laminate dielectric in a PCB. Herein, this approach is tested for verification using 3-D full-wave numerical simulations. These ERD layers with the appropriate complex permittivity are included in the modeling of stripline examples. The parameters of an ambient laminate dielectric refined from conductor roughness in the stripline are determined using differential extrapolation roughness measurement technique. The agreement of the results of 3-D full-wave modeling simulations and measurements on multiple test structures justifies the proposed approach. Based on the extracted ERD parameters “design curves” can be built and used in numerical simulations of PCB high-speed designs.

고속신호 무결성 분석을 통한 PCI Express Gen3 시스템 설계

PCI Express는 고속 차동신호를 사용한 점대점(point-to-point) 프로토콜로 시스템 설계 시 Eye Diagram을 통한 신호의 손실(Loss)과 지터(Jitter) 분석이 필요하다. 특히 PCI Express Gen3 물리 신호는 8Gbps의 고속 직렬신호로 고속신호분석에 의한 시스템 설계가 반드시 요구된다. 본 논문은 PCI Express Gen3 서버 연결망 스위치카드 시스템 제작을 통하여 고속 직렬신호의 토폴로지 추출, 채널분석, 채널의 S-파라미터 추출 및 송수신 버퍼를 포함한 시스템의 신호분석 시뮬레이션을 다룬다. 채널의 손실을 보안하기 위해 수신단 Eye diagram 분석을 통하여 송신 버퍼의 이퀄라이저 파라미터를 조정하여 송신단 최적의 De-emphasis와 Preshoot 파라미터 값을 시뮬레이션을 통하여 찾고 있다.

Use of electromagnetic simulation for signal integrity analysis of TFT interfaces in automotive human machine interface systems

This article discusses about the use of electromagnetic (EM) simulation for signal integrity (SI) design on the interface to a thin film transistor (TFT) display used in automotive human-machine- interface (HMI) cluster. As the display size increases, so does the operating frequency of the display. With that, signal integrity (SI) simulation has become an integral part of automotive design. In order to perform an SI analysis of such interface, information of the printed circuit board (PCB) and flexible printed circuit (FPC) cable are required. Hence, a brute force approach of simulation and analysing such interface is time-consuming. Given the iterative nature of such design work, this has significant impact on the time to market. In this paper, several key methods to reduce computational effort is discussed and evaluated. This includes the use of equivalent circuit models, different modelling methods for the PCB and FPC, and models conversion. A practical example is demonstrated using the various co-simulation approaches to achieve fast SI analysis without compromising on its accuracy.

위성통신 중계기에서의 FPGA를 이용한 Gigabit 시리얼 송수신기 설계

In this paper, we have proposed gigabit serial transceiver based on backplane architecture at the satellite communication digital transponder. The transponder supports the full combinational switching function with broadband multi-channel using programmable device - Xilinx space-grade Virtex-5 FPGA. In order to implement the switching function, GTX transceiver solution inside Virtex-5 FPGA is used. Also hardware implementation is simple because of no additional component. In order to use a GTX transceiver, signal integrity(SI) simulation of PCB design is essential. We investigate the characteristics of the S-parameter, eye diagram, channel jitter of GTX transmission line and conform that GTX Transceiver operates without error. Finally the proposed PCB design will be utilized at satellite communication digital transponder EQM-2(Engineering Qualification Model-2).

Study on Signal Integrity Simulation for High Speed Serial Rapid IO

With the increases of signal transmission rate in digital systems, the signal integrity becomes increasingly important in high-speed circuit design. During the hardware design of high-speed serial Rapid IO, signal integrity simulation of 5Gbps high-speed serial bus had been carried out by using Channel Analysis tools. Reliable data was formed by effectively analysis and evaluation of pre-simulation, the signal quality of high-speed serial Rapid IO was verified by post-simulation. The non-ideal design parameters were optimized by referring to the effective data obtained in pre-simulation. Signal quality has been greatly improved by parameters optimization. Signal integrity simulation analysis and verification of serial Rapid IO provides strong support for the design and significantly improves the efficiency of hardware design.

An efficient approximation for arbitrary port suppression of multiport scattering parameters

SUMMARY The multiport scattering (S-) parameter matrix is increasingly utilized to compose models of large bit-width interconnect systems with broadband characteristics (frequency range of zero to tens of gigahertz) to perform increasingly accurate signal-integrity and power-integrity simulations. The search for an optimal solution space often requires generation of S-parameter models of interconnect systems for various signal/ground pin mappings, a process that can be computationally costly if the structure is electromagnetically solved for each distinct pin mapping. To expedite this model-generation process, we propose a method in which an N-port structure is electromagnetically solved only once to yield an N × N S-matrix; then, a linear system is formulated and solved to yield an (N − M) × (N − M) post-suppressed S-matrix (where M is the number of suppressed ports). This approach results in significant computational savings through elimination of electromagnetic field-solver runs for each distinct pin mapping. Included in this paper is a discussion about the limitations of this technique and several numerical examples. Copyright © 2013 John Wiley & Sons, Ltd.

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.

Reduced-Order Parametric Behavioral Model for Digital Buffers/Drivers With Physical Support

In this paper, we present a new behavioral model for high-speed digital output buffers/drivers. In the conceived model, the output current's relationship with the output voltage is expressed as a summation of a static nonlinearity plus linear dynamics. This separation in the model format is supported by the measurements as well as the physical structure of a general driver circuit. This approach merges the features of equivalent circuit and parametric approaches to build a reduced-order parametric behavioral model which, compared to other published models, is more adequate to describe the device's electrical behavior from transient input-output data. A simple single-step identification procedure is conceived to extract a model that proved to be stable and capable of significantly improving the simulation speed and accuracy of prediction. Finally, the resulting model is validated in a realistic signal integrity simulation setup, and is compared to transistor-level models and to the state-of-the-art input-output buffer information specification model.