Method of Effective Roughness Dielectric in a PCB: Measurement and Full-Wave Simulation Verification

Abstract

Surface roughness topography of printed circuit boards (PCBs) needs to be included in signal integrity simulations in order to accurately predict the insertion loss of the structure and its delay time. An effective roughness dielectric (ERD) model can be used to substitute an inhomogeneous interface between copper foil and laminate dielectric in a PCB. Herein, this approach is tested for verification using 3-D full-wave numerical simulations. These ERD layers with the appropriate complex permittivity are included in the modeling of stripline examples. The parameters of an ambient laminate dielectric refined from conductor roughness in the stripline are determined using differential extrapolation roughness measurement technique. The agreement of the results of 3-D full-wave modeling simulations and measurements on multiple test structures justifies the proposed approach. Based on the extracted ERD parameters “design curves” can be built and used in numerical simulations of PCB high-speed designs.