Signal And Power Integrity Research Articles

A Statistical Approach for Signal and Power Integrity Co-Design in High-Speed Interconnects Considering Non-Linear Power/Ground Noise and Bit-Patterns.

In this article, a novel statistical approach is proposed and applied to co-design signal and power integrity (SI/PI) in high-speed interconnects considering the non-linear power/ground noise generated by parallel buffers and bit-patterns. With increased data rates and decreased operating voltages, the allowed noise margin in high-speed interconnects is continuously reduced, and this trend requires SI/PI co-design. Specifically, non-linear power/ground noise associated with simultaneous switching circuits sharing a power delivery network (PDN) and bit-patterns must be carefully considered during the interconnects' design and analysis phase. In many cases, conventional electromagnetic (EM) and transient circuit simulators require heavy computational resources or even fail to deliver an accurate result. The proposed statistical method estimates the statistical eye-diagram in the high-speed interconnect considering power/ground noise and bit-patterns such as data bus inversion (DBI) coding. The accuracy and computational efficiency of the proposed method are validated by comparing the result with HSPICE transient simulation result. The proposed method is also compared with conventional statistical methods, such as peak distortion analysis (PDA) and statistical channel simulation in the transient simulator. Lastly, the proposed method is applied to the SI/PI co-design and co-analysis in the high bandwidth memory (HBM) interposer channel. Impacts of decoupling capacitors on hierarchical PDN impedance, statistical eye-diagram of the HBM channel, and bit error rate (BER) Bathtub curves are summarized. Finally, the BER eye-diagram is derived from the estimated statistical eye-diagram for timing and voltage analysis. The impacts of hierarchical PDN design and bit-patterns on SI/PI are discussed.

Analysis of Pre-Driver and Last-Stage Power-Ground-Induced Jitter at Different PVT Corners.

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct DC supply voltages at the pre-driver (i.e., /) and last stage (i.e., ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

Resource allocation applied to flexible printed circuit routing based on constrained Delaunay triangulation

Flexible printed circuit (FPC) are widely used as connectors in compact package such as cellular telephones where required high performance. The increasing number of constrains makes manual routing an extremely complicated and time-consuming task. In this paper, we present a resource allocation framework which employs computational geometry considering signal and power integrity (SI/PI). To perform a reasonable resource allocation, we propose an escape-triangle-passage model (ETP model) based on constrained Delaunay triangulation (CDT). Experimental results on some industrial data show our strategy assembled routing channel for each group of nets has good robustness and is suitable for irregular polygonal routing region, significantly improving the routing quality and reducing iteration times.

Extraction of Single Cell Impedance From Battery Module Measurement by Simulation-Based De-Embedding

Batteries are a fundamental part of many modern electric systems. As a result, battery modeling is increasingly important for the prediction of signal and power integrity (SIPI) as well as electromagnetic compatibility (EMC). Conventional battery module modeling requires knowledge of the integrated cells first, which is usually obtained by measurement on single cells. However, if individual cells are not accessible, the single cell's impedance needs to be extracted from measurement of the complete module. This work describes two solutions to this problem, which are both based on 3D electromagnetic (EM) simulation of the battery module with surrogate cell models to obtain S-parameters which describe coupling effects inherent to the modules's geometry. By either fitting of the simulated module impedance to the measured data on circuit schematic level, or by numerical multiport de-embedding, the single cell impedance is extracted. Considered frequencies range from 9 kHz to 1 GHz.

SPI 2022 Held in Siegen, Germany

The Workshop on Signal and Power Integrity (SPI) was held from May 22–25, 2022 in Siegen, Germany. Organized by General Co-Chairs Elmar Griese and Thomas Kühler from the Institute of Theoretical Electrical Engineering & Photonics (University of Siegen), the Workshop was attended by 68 participants.

Scenes from the 2022 IEEE International Symposium on Electromagnetic Compatibility (EMC), Signal and Power Integrity (SIPI) in Spokane, Washington, August 1-5

Scenes from the 2022 IEEE International Symposium on Electromagnetic Compatibility (EMC), Signal and Power Integrity (SIPI) in Spokane, Washington, August 1-5

Foreword: Special Section on Packaging and Interconnects: Cutting-Edge Solutions in Modeling, Design, and Characterization—Part II

Following the previous issue of the IEEE Transactions on Components, Packaging, and Manufacturing Technology, this second part of the Transactions continues the Special Section on Packaging and Interconnects: Cutting-Edge Solutions in Modeling, Design, and Characterization. This special section is built from selected works that were initially presented at the IEEE Workshop on Signal and Power Integrity (SPI) 2018, the IEEE Conference on Electrical Performance of Electronic Packaging Systems (EPEPS) 2018, and the IEEE Electrical Design of Advanced Packaging Systems (EDAPS) Symposium 2018. The three conferences are cosponsored by the IEEE Electronics Packaging Society (EPS) and represent the ideal forums in Europe, North America, and Asia to exchange innovative ideas and discuss the state-of-the-art research and development of electrical modeling, design, and other related fields for packaging and interconnects.

Behavioral Modeling of Tunable I/O Drivers With Preemphasis Including Power Supply Noise

This article addresses the nonlinear behavioral modeling of tunable drivers with preemphasis including power supply noise. The proposed model relies on the use of state-aware weighting functions that control the transitions of the driver’s output stage for the scenarios where switched input logic states are shorter than the preemphasis duration, and the influence of supply voltage variation is considered. For the power supply noise analysis, the method is applied to multiple ports. Feedforward neural networks (FFNNs) are used to implement the state-aware weighting functions, and recurrent neural networks (RNNs) are used to capture the dynamic memory characteristics of driver’s ports. For tunable drivers in the state-of-the-art design covering features such as drive strength and preemphasis, a parameterized model that considers driver control parameters is presented. As a black-box approach, the resulting model protects intellectual property (IP). Practical industrial driver examples demonstrate the good accuracy, flexibility, and significant simulation speedup of the proposed model, which can facilitate the signal and power integrity (SIPI) analysis.

Introduction to the Special Issue for the 2017 IEEE International Symposium on EMC+SIPI

We are very pleased to present this special issue, which collects extended versions of the best scientific contributions presented at the IEEE International Symposium on Electromagnetic Compatibility (EMC), Signal and Power Integrity (SIPI), held in Washington, DC, USA, in August 2017. Among the novelties of this year’s edition, an “online symposium” was made available on the Internet to enable worldwide connection with the most important event of the IEEE EMC Society. In total, the symposium featured more than 180 regular papers, including oral and poster presentations. Special sessions, workshops/tutorials, panels, demonstrations, and abstract-reviewed papers that have an industry-oriented focus further enriched the technical program. A total number of 30 papers were selected from the regular papers and nominated for one of the three symposium awards (best EMC paper, best SIPI paper, and best student paper). We invited all the authors of these nominated papers to submit an extended version of their work. Our invitations and the subsequent peer-review process resulted in 13 accepted manuscripts. A wide range of subjects in EMC and SIPI are covered in these papers, which are grouped according to the usual categories of the IEEE Transactions on Electromagnetic Compatibility. To fulfill the high publication standard of the journal in terms of quality and significance, the authors had to include substantially new technical content beyond the symposium paper, and to place the obtained results in proper context with respect to the state of the art.

Guest editorial for the Special Issue on signal and power integrity of microelectronic networks through modelling and simulation of fields and devices

Today's mobile and interconnected society poses complex and growing challenges to the electronic systems that back emerging big data and Internet of Things technologies. As these systems execute increasingly complex algorithms and programs on vast datasets, ensuring their signal and power integrity (SPI) is essential to safeguarding their functionality and interoperability. The hardware systems that enable these advanced technologies and applications must be wireless, low-power/energy, high-speed, high-bandwidth, ultra-thin/small, scalable, reliable, and inexpensive. The design, optimization, fabrication, and testing of such hardware systems poses a formidable challenge spanning a variety of interdisciplinary fields while requiring the simultaneous modeling of coupled electrical, mechanical, and thermal responses of both passive interconnects and active devices. To further complicate matters, multi-physics models of these devices must be capable of quantifying uncertainty due to random variations in design, fabrication, and test processes, as well as (un)intentional noise in the environment. Ensuring the SPI of such electronic systems often requires high-fidelity (e.g., less than 10−6 field error) and full-wave quantification of the electromagnetic (information) waves. Modeling field propagation in such systems is nontrivial. Indeed, electromagnetic waves in these systems often propagate through multi-port networks of lossy, dispersive, inhomogeneous, multilayer (nonuniform), nonlinear, and multi-scale structures. The smallest features of these structures can range from nanometers on chip, to micrometers on package, to millimeters on system. In addition, the flow of signal and power across the complex spatial and temporal dimensions is influenced by thermal and power management specifications. Analytical methods are useful for modeling electromagnetic fields on simple and symmetric structures. While they oftentimes provide useful insights relating to the system response, used by themselves, they have limited range and scope. To solve problems of practical interest, computational electromagnetic (CEM) methods are indispensable. Although recent advancements in CEM methods have enabled solutions to problems considered nearly impossible only a decade ago, many practical applications remain out of the range of present-day algorithms. As a result, CEM practitioners are often forced to trade accuracy for computational cost (memory and time) while accepting an error that depends on the specific problem, the chosen CEM method, and the simplifying assumptions. This Special Issue provides a glimpse into new CEM trends for SPI problems. A Special Issue on this topic cannot be comprehensive; therefore, the intent is to motivate the reader to further explore the vast SPI literature, and to stimulate the development of novel and exciting research, publications, and tools that define the state-of-the-art in the field. Finally, the hope is to inform and generate awareness in the wider engineering community about the significant interdisciplinary challenges and the proportionally significant opportunities in this important and promising field. I'd like to extend my sincere gratitude to all authors for their high-quality contributions. I also would like to thank all reviewers for their invaluable time and efforts to improve the quality of the papers.

Foreword: Special Section on Addressing Signal and Power Integrity in Future Generation Systems—Part 2: Modeling Considerations

This Special Section is a collection of six articles highlighting the main directions that the researchers from academia and industry are exploring for managing signal and power integrity (SPI) through advanced modeling techniques. A previous Special Section (Part 1) on Addressing Signal and Power Integrity in Future Generation Systems presented eight papers in the two main categories of technological and design aspects. As in Part 1, the authors were selected by looking at the best papers presented at two major IEEE conferences dedicated to SPI topics that were held annually in the United States (EPEPS2015, San Jose, CA, USA) and Europe (SPI2016, Turin, Italy). Together, these two Special Sections give a good overview of leading research in advancing SPI in systems.

Foreword: Special Section on Addressing Signal and Power Integrity in Future Generation Systems—Part I: Technology and Design Considerations

Ensuring signal and power integrity (SPI) is a primary concern for the electronic packaging community. The continuous increase of operating frequencies, combined with more and more aggressive miniaturization and integration strategies, poses tremendous challenges to designers. Every transistor must receive power with reduced noise, and all signals must be received properly, despite the plethora of signal and power degradation effects due to crosstalk and electromagnetic interaction, losses, and dispersion due to material nonidealities, reflections due to mismatches, and discontinuities, just to name a few. Proper handling of such effects requires precise characterization through modeling, suitable design strategies to minimize them, and the technological ability to realize the design.

Two years of signal and power integrity in Italy: a report on SPI2016 and SPI2017

The IEEE Signal and Power Integrity (SPI) Workshop started in 1997 following an intuition of a group of researchers from the University of Hannover, Germany. At that time, it was already clear that interconnects were going to be one of the major limiters of system performance in the years to come. The first edition of the conference was thus named IEEE Workshop on Signal Propagation on Interconnects and took place in Travemunde, Germany, with a strong technical focus on understanding, modeling and simulating the physics of interconnects.

Present and future of I/O-buffer behavioral macromodels

Modern Signal and Power Integrity (SI/PI) verification flows rely on accurate models for complex I/O-buffers that drive and receive electrical signals on high-speed channels. The sheer density of modern integrated circuits makes detailed transistor-level descriptions computationally cumbersome to the point where they become unusable for systemlevel simulations. Fortunately, transistor-level descriptions may be replaced with more compact representations that approximate the input/output buffers behavior with considerable accuracy while providing a simulation speedup of several orders of magnitude. Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/ PI simulations. This paper presents an overview of the stateof- the-art in I/O-buffer behavioral modeling, introducing the main features of both standard and emerging solutions. Open issues and future research directions are also discussed.

Foreword: Special Section on RF, 3-D-ICs and Interconnects

The seven papers in this special section are updated and expanded versions of the papers that appeared in the IEEE CPMT-sponsored conferences: Electrical Performance of Electronic Packaging and Systems (EPEPS) 2011 and 2012, and Workshop on Signal and Power Integrity (SPI) 2011 and 2012.

Foreword: Special Section on “Macromodeling and Variability Analysis for Signal and Power Integrity”

The seven papers in this special section are updated and expanded versions of the papers that appeared in the IEEE CPMT-sponsored conferences: Electrical Performance of Electronic Packaging and Systems (EPEPS) 2011 and 2012, and Workshop on Signal and Power Integrity (SPI) 2011 and 2012.