Sigma-delta Modulated Signals Research Articles

Analysis and simulation of a novel speed estimation method based on oversampling and noise shaping techniques

Angle measurement is widely used in the servo positioning and speed control of electrical drives, where optical encoders are employed as sensors and coupled to microcontrollers with complex peripherals to provide effective position and speed measurement methods. These methods can achieve high precision and fast response, but are not particularly efficient with computer resources and require high computational costs. Therefore, fast timers, encoder signal oversampling, and a complex post-processing algorithm are used together in a recent research work to achieve a high-precision speed estimation method. Our work will prove that encoder outputs share the oversampling and noise shaping properties typical of sigma-delta modulated signals if they are sampled regularly. Based on this, a new simple and accurate speed estimation method is proposed. Here, encoder outputs are synchronously sampled, differenced, and low-pass filtered. As a result, the speed estimation circuit and its interface with the control unit are greatly simplified, while high accuracy can be achieved. A detailed mathematical analysis of the proposed technique is also performed, and the results obtained are validated by means of a simulation environment using Matlab&Simulink.

Distributed Antenna System Using Sigma-Delta Intermediate-Frequency-Over-Fiber for Frequency Bands Above 24 GHz

The fifth generation (5G) cellular network is expected to include the millimeter wave spectrum, to increase base station density, and to employ higher-order multiple-antenna technologies. The centralized radio access network architectures combined with radio-over-fiber (RoF) links can be the key enabler to improve fronthaul networks. The sigma-delta modulated signal over fiber (SDoF) architecture has been proposed as a solution leveraging the benefits of both digitized and analog RoF. This work proposes a novel distributed antenna system using sigma-delta modulated intermediate-frequency signal over fiber (SDIFoF) links. The system has an adequately good optical bit-rate efficiency and high flexibility to switch between different carrier frequencies. The SDIFoF link transmits a signal centered at a 2.5 GHz intermediate frequency over a 100 m multi-mode fiber and the signal is up-converted to the radio frequency (24–29 GHz) at the remote radio unit. An average error vector magnitude (EVM) of 6.40% (−23.88 dB) is achieved over different carrier frequencies when transmitting a 300 MHz-bandwidth 64-QAM OFDM signal. The system performance is demonstrated by a 2 × 1 multiple-input single-output system transmitting 160 MHz-bandwidth 64-QAM OFDM signals centered at 25 GHz. Owing to transmit diversity, an average gain of 1.12 dB in EVM is observed. This work also evaluates the performance degradation caused by asynchronous phase noise between remote radio units. The performance shows that the proposed approach is a competitive solution for the 5G downlink fronthaul network for frequency bands above 24 GHz.

Distributed Multi-User MIMO Transmission Using Real-Time Sigma-Delta-Over-Fiber for Next Generation Fronthaul Interface

To achieve the massive device connectivity and high data rate demanded by 5G, wireless transmission with wider signal bandwidths and higher-order multiple-input multiple-output (MIMO) is inevitable. This work demonstrates a possible function split option for the next generation fronthaul interface (NGFI). The proof-of-concept downlink architecture consists of real-time sigma-delta modulated signal over fiber (SDoF) links in combination with distributed multi-user (MU) MIMO transmission. The setup is fully implemented using off-the-shelf and in-house developed components. A single SDoF link achieves an error vector magnitude (EVM) of 3.14% for a 163.84 MHz-bandwidth 256-QAM OFDM signal (958.64 Mbps) with a carrier frequency around 3.5 GHz transmitted over 100 m OM4 multi-mode fiber at 850 nm using a commercial QSFP module. The centralized architecture of the proposed setup introduces no frequency asynchronism among remote radio units. For most cases, the 2 × 2 MU-MIMO transmission has little performance degradation compared to SISO, 0.8 dB EVM degradation for 40.96 MHz-bandwidth signals and 1.4 dB for 163.84 MHz-bandwidth on average, implying that the wireless spectral efficiency almost doubles by exploiting spatial multiplexing. A 1.4 Gbps data rate (720 Mbps per user, 163.84 MHz-bandwidth, 64-QAM) is reached with an average EVM of 6.66%. The performance shows that this approach is feasible for the high-capacity hot-spot scenario.

Comparison Between Analog Radio-Over-Fiber and Sigma Delta Modulated Radio-Over-Fiber

With the continuously increasing demand of cost effective, broadband wireless access, radio-over-fiber (RoF) starts to gain more and more momentum. Various techniques already exist, using analog (ARoF) or digitized (DRoF) radio signals over fiber; each with their own advantages and disadvantages. By transmitting a sigma delta modulated signal over fiber (SDoF), a similar immunity to impairments as DRoF can be obtained while maintaining the low complexity of ARoF. This letter describes a detailed experimental comparison between ARoF and SDoF that quantifies the improvement in linearity and error vector magnitude (EVM) of SDoF over ARoF. The experiments were carried out using a 16-QAM constellation with a baudrate from 20 to 125 MBd modulated on a central carrier frequency of 1 GHz. The sigma delta modulator runs at 8 or 13.5 Gbps. A high-speed vertical-cavity surface-emitting laser (VCSEL) operating at 850 nm is used to transmit the signal over 200-m multimode fiber. The receiver amplifies the electrical signals and subsequently filters to recover the original RF signal. Compared with ARoF, improvements exceeding 40 dB were measured on the third order intermodulation products when SDoF was employed, the EVM improves between 2.4 and 7.1 dB.

A Sigma-Delta Domain Lowpass Wave Filter

This paper presents a sigma-delta (SD) domain lowpass wave filter modeled after an analog distributed parameter filter (ADPF). The SD domain filter operating on SD modulated signals is built with two kinds of units, shift registers on which two-level-quantized waves propagate and sorter-based units that simulate reflection, transmission, and superposition of waves propagating on the transmission lines of the ADPF. The SD domain lowpass filter has the following advantages: First, design techniques for ADPFs can be applied directly to the SD domain filter. Secondly, the SD domain filter consists mainly of shift registers and sorting networks. Because the structures of the registers and the networks are spatially uniform and their internal connections are local, the filter architecture will mitigate difficulties in physical design and fabrication of filter circuits using nanometer-scale quantum effect devices. We confirmed by computer simulation that the designed SD domain filter possessed the same frequency response characteristics as the theoretical characteristics of the reference ADPF. Although internal units of SD domain filters generate SD modulation noise, it does not change to aliasing noise in the signal band because the operations of the units are linear. Therefore, the quantization noise contained in the outputs of SD domain filters is shaped like SD modulation noise.

A 4 GHz CMOS multiplier for sigma—delta modulated signals

An integrated circuit design of a high speed multiplier for direct sigma—delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier's stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier's noise performance is also presented.

Sequence characteristics of multi-level and second-order sigma-delta modulated signals

Sequence characteristics of multi-level and second-order sigma-delta modulated signals

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations

We construct arithmetic modules for signal processing with sigma-delta modulated signal form which has advantage in signal quality over other pulsed signal forms. In the first part of this paper, adders and exponential function modules are presented first and secondly. By utilizing the two modules, several transcendental functions including hyperbolic and logarithmic functions are constructed. The exponential functions and logarithmic functions provide log-domain arithmetic operations including multiplication, division, and power functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the arithmetic operations on any form of sigma-delta modulated signals. These modules, together with algebraic functions to be presented in the second part of this paper, organize an extensive module library for the sigma-delta domain signal processing.

Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part II: Multiplication and Algebraic Functions

We construct arithmetic modules for signal processing with sigma-delta modulated signal form which has advantage in signal quality over other pulsed signal forms. In the second part of this paper, multi-input multipliers are presented first. Secondly, dividers and square root function modules with the multiplier on their internal feedback path are constructed. Combined use of the multipliers, dividers, and the square root functions creates various algebraic functions including polynomial and rational functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the algebraic operations on any form of SD modulated signals. These modules, together with transcendental functions presented in the first part of this paper, organize an extensive module library for the sigma-delta domain signal processing. The multiplier output contains noise components which originate from quantization. The noise power can decrease in exchange for circuit complexity. A time-division multiplexing technique based on N-tone sigma-delta modulation is applied to the multipliers for reducing the complexity. Signal processing circuits built of nanometer-scale quantum effect devices must be equipped with fault tolerance of transient device error. By computer simulation of a multiplier built of single-electron tunneling devices, we found that the multiplier decreased its output SNDR from 43 to 27 dB at an OSR of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> as the device error rate increased from 0 to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . However, the multiplier was never functionally failed during the simulation.

A sigma–delta analog to digital converter based on iterative algorithm

In this article, we present a new iterative algorithm aimed at improving the performance of the sigma–delta analog to digital (A/D) converter. We subject the existing sigma–delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma–delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to operate at high frequency levels with optimized power consumption and small chip area. Implementation of the design with an FPGA shows that experimental results are in agreement with the simulation results.

Realization of Ternary Sigma-Delta Modulated Arithmetic Processing Modules

Sigma-delta modulated systems have a number of very appealing properties and are, therefore, heavily used in analog to digital converters, amplifiers, and modulators. This paper presents new results which indicate that they may also have significant potential for general purpose arithmetic processing. The paper introduces new arithmetic processing structures for ternary (i.e., +1, 0, or -1) sigma-delta modulated signals. Simulations show that these new structures can be implemented very efficiently and have relatively good accuracy.

Quad-level bit-stream adders and multipliers with efficient FPGA implementation

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76% hardware savings) and faster (>93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables.

Bit-Stream Adders and Multipliers for Tri-Level Sigma–Delta Modulators

We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.

Direct projection decoding algorithm for sigma-delta modulated signals

Usually, sigma-delta modulators (/spl Sigma//spl Delta/M) are modeled by replacing the quantizer with an additive white noise source. Based on this linear model, linear decoder structures can be designed. However, the /spl Sigma//spl Delta/M is a nonlinear system, and corresponding nonlinear decoder structures may be able to achieve a better signal-to-quantization-noise ratio (SQNR) performance. In this paper, a new nonlinear decoding algorithm is presented. It is based on the projection onto complex sets (POCS) algorithm developed by Hein and Zakhor. Our algorithm reduces the decoding problem to the solution of a single quadratic programming problem based on the state equations of the modulator and the condition that the modulator input signal is bandlimited. The bandlimitation constraint is directly applied to the state equations. Thus, the resulting quadratic programming problem needs to be solved only once.

IIR filtering on sigma-delta modulated signals

A design methodology for realising IIR filters on sigma-delta modulated signals is proposed. It is shown that only 3N adders together with minor logic are required to implement an Nth order filter. This type of filtering should prove useful in VLSI technologies where interfaces to analogue signals are required.