Realization of Ternary Sigma-Delta Modulated Arithmetic Processing Modules

Amin Z Sadik,Peter J O'Shea

doi:10.1155/2009/574627

Abstract

Sigma-delta modulated systems have a number of very appealing properties and are, therefore, heavily used in analog to digital converters, amplifiers, and modulators. This paper presents new results which indicate that they may also have significant potential for general purpose arithmetic processing. The paper introduces new arithmetic processing structures for ternary (i.e., +1, 0, or -1) sigma-delta modulated signals. Simulations show that these new structures can be implemented very efficiently and have relatively good accuracy.

Highlights

Oversampled sigma-delta modulation (SDM) signal representations have several key advantages over traditional Nyquist rate pulse code modulated formats
This is so because within many systems, the “front end” analog to digital converters and “back end” digital to analog converters use SDM bitstream format, but the intermediate processing stages are typically implemented in multibit format
This section proposes an efficient new structure for binary to ternary format conversion, with this new structure involving an SDM whose internal integrator is formed from the adder proposed in the previous section

Summary

Introduction

Oversampled sigma-delta modulation (SDM) signal representations have several key advantages over traditional Nyquist rate pulse code modulated formats. Ternary arithmetic processing modules are proposed, and an attempt is made to provide a measure of the accuracy of these systems This is done by determining the resolution or number of bits in a multibit counterpart with similar accuracy. The quantization noise at the output of the basic ternary adder has two components: (i) the quantization noise inherent in the two input signals and (ii) the quantization noise due to the truncation operation which occurs when the two inputs have identical values. The total power spectral density at the output of the adder will be the sum of the quantization noise corresponding to the two input signals (2Pq( f )) and Ptrun( f ). The subtraction operation can be accomplished by negating one of the ternary bitstreams and using the same proposed adder

Improved Adder

Format Conversion via an SDM with Ternary Integrator

Simulations

Conclusions