Abstract
In this article, we present a new iterative algorithm aimed at improving the performance of the sigma–delta analog to digital (A/D) converter. We subject the existing sigma–delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma–delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to operate at high frequency levels with optimized power consumption and small chip area. Implementation of the design with an FPGA shows that experimental results are in agreement with the simulation results.
Highlights
Analog to digital (A/D) convertors are key in many applications of digital signal processing (DSP) and communication systems [1]
In a sigma–delta modulator (SDM), the original signal is highly oversampled and the internal clock operates at a much higher rate than the bandwidth of the signal; the oversampled signal is downsampled at the last stage of the A/D conversion
We discover that the iterative algorithm enhances the performance of Sigma–Delta A/D converters for different types of low-pass filter (LPF) and the numbers of quantization bits
Summary
Analog to digital (A/D) convertors are key in many applications of digital signal processing (DSP) and communication systems [1]. Conventional A/D converters consist of two steps: a sampling operation followed by a digital quantization. A common clock is operated in order to convert analog signals to digital values [2,3]. The iterative method is used to decrease the distortion caused by modulator. This innovative approach can be implemented without any changes to the structure of the SDM by adding a mathematical block after the demodulator of the SDM.
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