2+2 Switched-Current Delta-Sigma Modulator with Digital Noise Cancellation Circuit

Abstract

This paper proposes a 2+2 switched-current (SI) multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a digital noise-cancellation circuit (DNCC) by using a TSMC 0.18 μm 1P6M CMOS process. In view of area-efficiency, the current-mode sample-and-hold circuit (S/H) is designed to reduce the chip area considerably. It plays a vital role in the performance of the DSM. Note that the input impedance of the modified current-mode feedback memory cell (FMC) is decreased by [2 + (g'm3/gml-1) x A] times relative to a traditional FMC and the input current is being processed more quickly. However, it suffers the transmitted error particularly for small input currents. The MASH architecture inherited a superior signal-to-noise-and-distortion ratio (SNDR) by using an effective digital noise cancellation circuit (DNCC) and a low-pass filter varied from 10 Hz to 20 kHz. The designed current-mode DNCC is composed of six delay components using master-slave D flip-flop and a logic circuit using the karnaugh map. Post-layout simulations reveal that the simulated SNDR was 90.4 dB and the ENOB was 14.73 bits. The designed IC consumes 18.19 mW at a chip area of 0.13 mm2 and a simulated FoM of 24.5 pJ/conv. The advantages of our modulator are its small chip area and high processing speed at all input currents.