Abstract
This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta-sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process. In view of area efficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by [2 + (g' <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m3</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m1</sub> - 1) x A] times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master-slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits-at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.
Highlights
The key motivation of this study is to develop a new highorder switched-current multistage-noise-shaping (SI MASH) delta–sigma modulator (DSM) with a digital noisecancellation circuit (DNCC) for applications in motor drive systems, whose bandwidths vary from dc to a few several kilohertz
In view of the design of delta-sigma analog-to-digital converters (ADCs), a 4th-order SI MASH DSM is proposed with a simplified DNCC because of its small chip area
By integrating a modified feedback memory cell (FMC) with a cross-connected bias circuit, the post-layout simulation proved that the signal-to-noise ratio (SNR) was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits at a sampling rate of 10.24 MHz, an oversampling ratio (OSR) of 256, and a signal bandwidth of 20 kHz
Summary
The key motivation of this study is to develop a new highorder switched-current multistage-noise-shaping (SI MASH) delta–sigma modulator (DSM) with a digital noisecancellation circuit (DNCC) for applications in motor drive systems, whose bandwidths vary from dc to a few several kilohertz (kHz). In view of the design of delta-sigma ADC, a 4th-order SI MASH DSM is proposed with a simplified DNCC because of its small chip area. An effectively designed MASH architecture can deliver a high signalto-noise and distortion ratio (SNDR) if its designers correctly considered process variations, thermal noise types, and quantization errors [8] To counteract this mismatch, the analog circuit must be carefully designed. The features of this study’s device are excellent SNR, a small chip area, and a high figure of merit (FoM)—from the current-mode S/H circuit with modified FMC, cross-connected bias circuit, and simplified DNCC. If one integrates the non-overlapping clocks, φ1 and φ1, with the specifications of a sample-and-hold circuit (S/H), the desired sample-and-hold circuit can be implemented with a pair of FMCs
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