SiGe Power Amplifier Research Articles

Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM

Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM

A 4.4-6.4-GHz compact SiGe power amplifier with 30.5-dBm psat and 34.8% PAE based on triple-tank power combiner

A 4.4-6.4-GHz compact SiGe power amplifier with 30.5-dBm psat and 34.8% PAE based on triple-tank power combiner

A compact SiGe D-band power amplifier for scalable photonic-enabled phased antenna arrays

To address the rising demand for high-speed wireless data links, communication systems operating at frequencies beyond {100},hbox {GHz} are being targeted. A key enabling technology in the development of these wireless systems is the phased antenna array. Yet, the design and implementation of such steerable antenna arrays at frequencies over {100},hbox {GHz} comes with a multitude of challenges. In particular, the cointegration of active electronics at each antenna element poses a major hurdle due to the inherent space constraints in the array. This article proposes a novel scalable concept for opto-electronic phased antenna arrays operating at 140 GHz. It details the system architecture of a transmitter that enables the implementation of large scale, wideband, 2D steerable phased antenna arrays and presents the design and measurement of a compact SiGe power amplifier (PA) chip to be used as one of its key building blocks. The amplifier achieves a gain of 20 dB at 135 GHz, features a P_{1dB} of 14.6 dBm and can support data rates up to 45 Gbps in a limited footprint of only 540μm × 550μm. This makes it one of the fastest, most powerful D-band power amplifiers in literature with a footprint compatible with frac{lambda }{2}-spaced phased array integration.

A Broadband SiGe HBT Cascode Power Amplifier Achieving Watt-Level Peak Output Power With 38.6% PAE and 90.9% Large-Signal Fractional Bandwidth

This brief presents a broadband SiGe power amplifier that achieves 30.1 dBm peak <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{SAT}$ </tex-math></inline-formula> , 38.6% peak power-added efficiency (PAE), 90.9% large-signal fractional bandwidth (FBW) and a 3 dB bandwidth from 5.4 to 13.8 GHz. A balanced topology with two-stage, four-way combing is utilized to achieve watt-level output power and high-power efficiency in a wide range of operating frequency. Power stage is optimized and simulated from the perspective of high output power. At the output stage, a 90° coupler and two transformers are co-optimized for broadband output power combining as well as power matching. This balanced PA is implemented in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu }\text{m}$ </tex-math></inline-formula> SiGe BiCMOS process with a chip area (with pads) of 2.31 mm2.

A 44 To 64 GHz Broadband 90° Hybrid Doherty PA With Quasi Non-Foster Tuner in 0.13 μm SiGe

This letter presents a simultaneous broadband and back-off efficient mm-wave linear Doherty PA utilizing quadrature hybrid and a Doherty bandwidth enhancement technique exploiting quasi non-Foster impedance synthesis at the quadrature isolation port. We show analytically the design methodology of the non-Foster synthesis with ON-chip impedance tuner that allows broadband back-off efficiency, without suffering from nonlinearity due to the low-leakage power of the isolated port. Across 44-64 GHz, the proposed SiGe PA achieves collector efficiency of 26%-34.7% at peak power and 14%-23.2% at 6 dB back-off with 18.5-21.5 dBm Psat and peak gain of 18.5 dB. It supports 6 Gbps 64 QAM signal with -26.5 dB/-28.3 dBc EVM/ACLR at average Pout/PAE of 14.6 dBm/14.6% at 54 GHz. To the best of the authors' knowledge, this work achieves highest bandwidth among silicon-based mm-wave power amplifiers (PAs) where higher than class-B back-off efficiency is achieved.

A SiGe Power Amplifier With Double Gain Peaks Based on the Control of Stationary Points of Impedance Transformation

A broadband SiGe power amplifier (PA) with double gain peaks for 5G applications is presented. The differential structure is widely adopted in millimeter-wave circuit design to decrease the impact of the source parasitic inductance that is induced by the bonding wires. Since differential PA results in a higher impedance transformation ratio of the matching network, differential PAs generally have narrower bandwidth than single-ended PAs. Through the bandwidth analysis of the matching network, the transformer used for interstage matching is elaborately designed to ease gain fluctuations. By controlling the stationary points of impedance transformation, the maximum available gain characteristic of a transistor, which decreases with increasing frequency, can be compensated. The gain curve of PA, thus, has double gain peaks within operational frequencies to make its frequency responses as flat as possible. The proposed PA for the frequency band from 27 to 37 GHz is fabricated in a standard 130-nm SiGe BiCMOS process, which occupies 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under the 2.5-V voltage supply, the SiGe PA exhibited a power gain of 33.5 dB and output power of 21.3 dBm with 24% power-added efficiency at 31 GHz. It achieves a 34% 3-dB small-signal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S_{21}$ </tex-math></inline-formula> bandwidth from 27.3 to 38.5 GHz.

A 30-to-41 GHz SiGe Power Amplifier With Optimized Cascode Transistors Achieving 22.8 dBm Output Power and 27% PAE

In this brief, A two-stage power amplifier (PA) with a four-way series-parallel power combiner is presented for Ka-band applications. A compact power stage with optimized cascode transistors is proposed to minimize the parasitic effects and boost the amplifier output power at the mm-wave frequencies. The output network employs two spiral transformers and a transmission-line combiner to realize low-loss power matching and broadband series-parallel combining. The PA is fabricated in a 130-nm SiGe BiCMOS technology and it occupies a core area of 0.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The PA achieves a peak gain of 25.3 dB with the 3-dB bandwidth of 30-to-41 GHz. At the frequency of 35 GHz, the measured saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ), 1-dB compressed power (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ), and power-added efficiency (PAE) are 22.8 dBm, 22.6 dBm, and 27%, respectively.

A 60-GHz SiGe Power Amplifier With Three-Conductor Transmission-Line-Based Wilkinson Baluns and Asymmetric Directional Couplers

A compact, 60-GHz high-power, wideband balanced power amplifier, implemented in a 90-nm SiGe BiCMOS technology, is demonstrated. A three-conductor transmission-line-based asymmetric coupled-line directional coupler is used to achieve impedance transformation and quadrature power combining simultaneously. A Wilkinson balun based on a three-conductor transmission line structure is implemented to achieve a four-way series-parallel power combining. Analyses of the three-conductor asymmetric coupler and the Wilkinson balun combiner are provided in this article. The design achieved 17.3-dB small-signal gain, with 41.8-GHz 3-dB bandwidth, from 28.1 to 69.9 GHz. A 24.4-dBm saturated output power (PSAT) was measured at 60 GHz with a 22-GHz 1-dB P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> bandwidth, covering 45-67 GHz. The circuit showed a peak power-added efficiency (PAE) of 14.2% at 60 GHz, and the peak PAE is above 11.5% across the 1-dB P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> bandwidth. The proposed eight-way power combining scheme achieves 0.077-mm2 per-way area consumption and 449-mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> power density.

A Sandwiched-Slab-Transformer-Based SiGe Power Amplifier Operating at W- and D-Bands

In this letter, a 75.1–151.4-GHz silicon power amplifier (PA) is devised with the help of sandwiched slab transformer, which is proposed to increase the tuning ranges of coupling coefficient, quality factor, and conductivity. Being compact in size and simple in implementation enables it to be well-applied in multiple-way power combination. Based on this device, the fabricated PA in the 130-nm silicon germanium (SiGe) process demonstrates more than 14.1-dB gain at full $W$ -band and 77% of the $D$ -band. From 75 to 117.7 GHz, its measured $P_{\mathrm {sat}}$ is all above 16.8 dBm, while its peak point is 19.8 dBm at 100 GHz with 8.8% PAE.

Compact Layout Redesign of Output Matching Network of a 5.8-GHz SiGe Power Amplifier

This letter presents a general design methodology for compact layout of lumped element radio frequency (RF)/microwave matching networks based on partially overlapped inductors. We demonstrate the compact layout design approach on the output matching network of a TowerJazz 5.8-GHz SiGe power amplifier (PA) IP block fabricated in the 180-nm SBC18QH process. Our redesigned matching network achieves approximately a 20% footprint reduction. Small-signal measurements of PAs with original and compact output matching network designs, respectively, show virtually identical broadband performance.

A Compact, Wideband, and Temperature Robust 67–90-GHz SiGe Power Amplifier With 30% PAE

This letter presents the design of a compact, wideband, and high-efficiency $E$ -band power amplifier, integrated in a 0.13- $\mu \text{m}$ BiCMOS process and occupying 0.3 mm2. It consists of a single-stage balanced amplifier, with HBT transistors in cascode configuration. The power amplifier (PA) is biased in class AB, with a dc consumption of 156 mW. A compact bias circuit is employed to achieve temperature robustness, while the layout is optimized for wideband and highly efficient operation. Measurements show a peak power gain of 15.3 dB at 83 GHz, with a 29.3% fractional bandwidth and less than 1-dB degradation over a 25 °C–85 °C temperature range. The peak output power at saturation and 1-dB compression is 18.6 and 13.6 dBm, respectively, and the maximum power-added efficiency (PAE) is 30.7%.

Inverse class‐FX‐band SiGe HBT power amplifier with 44% PAE and 24.5 dBm peak output power

ABSTRACTAn X‐band power amplifier (PA) implemented in a silicon‐germanium (SiGe) heterojunction bipolar transistor technology is presented. The SiGe PA was designed for inverse class‐F mode using thin‐film microstrip (TFMS) lines, eliminating the use of conventional band‐limiting lumped inductors and transformers. Thus, simultaneous high efficiency and minimized in‐band variation were achieved for X‐band (8–12 GHz) applications. In addition, for boosting peak output power (Pout), the common‐base transistor in the PA core was designed to operate in a weak avalanche region, which allowed dynamic collector‐to‐base voltage to swing beyond the collector‐base breakdown voltage with open emitter without performance degradation. The fabricated SiGe PA demonstrates a high power‐added efficiency (PAE) of 43.2% and a peak Pout of 24.3 dBm at 10 GHz. Benefitting from the utilization of TFMS lines, the PA exhibits a flat response for both PAE (33.3–44%) and peak Pout (23.1–24.5 dBm) for the entire X‐band frequency range. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2868–2871, 2016

A Multimode SiGe BiCMOS 5–6 GHz Front-End IC that Enables 802.11ac Wave 2 and 802.11ax Wireless LAN Front-End Designs

A multimode 4.9–5.9 GHz ultra-linear single chip front-end integrated circuit (FEIC) for 802.11ac and emerging multi-gigabit per second (Gbps) wireless local area network (WLAN) applications is presented. The design is based on SiGe BiCMOS and realized in a 2.0 x 2.0 x 0.5 mm3 package. The FEIC design consists of both transmit (Tx) and receive (Rx) chains, which integrates a single-pole double-throw (SPDT) Tx/Rx CMOS switch, a SiGe power amplifier (PA), and a SiGe low noise amplifier (LNA) with a CMOS bypass attenuator. The SiGe PA in the transmit chain integrates input and output matching networks, harmonic filters, out-of-band rejection filters, supply voltage regulator and multi-mode bias circuits, temperature and voltage compensated power detector with on-chip directional coupler, and CMOS-compatible enable circuitry. The PA is controlled by the on-chip temperature and voltage compensated bias controller. With a 5 V supply, the transmit chain features 31 dB gain and excellent linearity. The transmit chain can deliver 19 dBm output power with current consumption 220 mA meeting below -40 dB Dynamic Mode Error Vector Magnitude (DEVM) for 1024 QAM signals and 20 dBm with current consumption 250 mA meeting below -35 dB DEVM for 256 QAM signals. The feature of ultra-low DEVM enables the emerging 1024-QAM applications. The harmonics emissions of the transmit chain can achieve below -50 dBm/MHz, greatly exceeding FCC out-of-band emission requirements. In addition, the linearity of the transmit chain output power is well scaled with the supply voltage from 3.0 V to 5.5V and insensitive to signal modulation bandwidths as well as duty cycles. The low linearity mode features 50 mA lower current consumption comparing to the high linearity mode. With the use of digital pre-distortion (DPD), it can achieve the similar linear power with 50 mA current reduction. The integrated log detector with an on-chip directional coupler ensures the accurate power control over 24 dB with less than 0.5 dB power control inaccuracy under VSWR 3:1 mismatch, which significantly increases the dynamic range and accurate power control for the transmit path. The Rx chain features noise figure (NF) below 2.5 dB with 15 dB gain and the current consumption of 8 mA as well as 8 dBm IIP3. The receive chain also integrates an 8 dB bypass attenuator having 25 dBm IIP3 with 3uA current consumption, which can prevent the WLAN radio from saturation under high field strength illuminations. All these unique features provide a turn-key solution for the single band or dual-band 802.11ac radio front-end circuits and emerging multiple gigabits per second high linearity WLAN radio designs. Figure 1

A Class-E Tuned W-Band SiGe Power Amplifier With 40.4% Power-Added Efficiency at 93 GHz

A W-band power amplifier with Class-E tuning in a 0.13 $\mu{\rm m}$ SiGe BiCMOS technology is presented. Voltage swing beyond $BV_{\rm CBO}$ is enabled by the cascode topology, low upper base resistance, and minimally overlapping current-voltage waveforms. At 93 GHz with 4.0 V bias, the peak power-added efficiency and saturated output power are measured to be 40.4% and 17.7 dBm, respectively. With the bias increased to 5.2 V, the peak power-added efficiency and saturated output power at 93 GHz are measured to be 37.6% and 19.3 dBm, respectively.

A Broadband 4.5–15.5-GHz SiGe Power Amplifier With 25.5-dBm Peak Saturated Output Power and 28.7% Maximum PAE

This paper presents the design of a broadband power amplifier (PA) in 130-nm SiGe BiCMOS technology. First, a single-stage broadband single-cell PA covering the 4.5–18-GHz frequency band is introduced. In this frequency range, this single cell achieves a measured gain, saturated output power $({ P}_{\rm sat})$ , output 1-dB compression point $({ P}_{1{\rm dB}})$ , and power-added efficiency (PAE) in the range from 12.8 to 15.7 dB, 18.8 to 23.7 dBm, 16.7 to 19.5 dBm, and 11.4 to 31.9%, respectively. Its peak saturated output power and maximum PAE are both obtained at 8.5 GHz. Second, to increase the output power, a PA consisting of two parallel broadband cells with a power combination is presented. This PA operates in the 4.5–15.5-GHz frequency range with measured gain, ${ P}_{\rm sat}, { P}_{1{\rm dB}}$ , and PAE in the range from 11 to 16.6 dB, 21.3 to 25.5 dBm, 18.7 to 21.7 dBm, and 11.9 to 28.7%, respectively. It achieves its peak saturated output power of 25.5 dBm at 8.5 GHz and its maximum PAE of 28.7% with an associated output power of 23.6 dBm at 6.5 GHz. Each of those two PAs achieves better performances than the state-of-the-art in broadband SiGe technology when comparing the output power level and efficiency.

A high-linearity SiGe RF power amplifier for 3 G and 4 G small basestations

This article presents the design and evaluation of a linear 3.3 V SiGe power amplifier for 3 G and 4 G femtocells with 18 dBm modulated output power at 2140 MHz. Different biasing schemes to achieve high linearity with low standby current were studied. The adjacent channel power ratio linearity performance with wide-band code division multiple access (3 G) and long term evolution (4 G) downlink signals were compared and differences analysed and explained.

A SiGe Envelope-Tracking Power Amplifier With an Integrated CMOS Envelope Modulator for Mobile WiMAX/3GPP LTE Transmitters

This paper presents a SiGe envelope-tracking (ET) cascode power amplifier (PA) with an integrated CMOS envelope modulator for mobile WiMAX and 3GPP long-term evolution (LTE) transmitters (TXs). The entire ET-based RF PA system delivers the linear output power of 22.3/24.3 dBm with the overall power-added efficiency of 33%/42% at 2.4 GHz for the WiMAX 64 quadrature amplitude modulation (64QAM) and the 3GPP LTE 16 quadrature amplitude modulation, respectively. Additionally, it exhibits a highly efficient broadband characteristic for multiband applications. Compared to the conventional fixed-supply cascode PA, our ET-based cascode PA meets the WiMAX/LTE spectral mask and error vector magnitude spec at close to its P1dB compression without the need of predistortion. The SiGe PA and the CMOS envelope modulator are both designed and fabricated in the TSMC 0.35-μm SiGe BiCMOS process on the same die. This study represents an essential integration step toward achieving a fully monolithic large-signal ET-based TX for wideband wireless applications.

RF Model and Verification of Through-Silicon Vias in Fully Integrated SiGe Power Amplifier

This letter proposes an RF model of through-silicon via (TSV) considering both skin-depth and lossy substrate effects up to 20 GHz. The TSV is fabricated in 0.18-μm SiGe BiCMOS process with the dimensions of 50 μm in diameter and 100 μm in depth. The equivalent circuit model is extracted from the measured results and physical structure of a single TSV. The frequency-dependent characteristics of TSV can be completely modeled by frequency-independent lumped elements through parameter extraction. Furthermore, a fully integrated SiGe power amplifier (PA) with TSVs is designed to verify the accuracy of the RF model of TSV. Meanwhile, a PA without TSVs is fabricated to compare the performance of the PA with TSVs. Due to the low parasitic impedance of TSVs, the PA with TSVs achieves better performance than that without TSVs, where the improvement is 0.5 dB in power gain and 2% in power-added efficiency, respectively.

Fully integrated low-power SiGe power amplifier for biomedical applications

A full-integrated very low-power SiGe power amplifier (PA) is realised using the innovations for high performance, 0.25 mu m SiGe process. The behaviour of the amplifiers has been optimised for the 2.1-2.4 GHz frequency band for a higher 1 dB compression point and high efficiency at a lower supply voltage. The PA delivers an output power of 3.75 and 1.25 mW for 2 and 1 V, respectively. The PA measurements yielded the following parameters: gain of 13 dB, 1 dB compression point of 5.7 dBm, and power added efficiency of 30% for 2 V supply voltage. The PA circuit can go down to 1 V of supply voltage with a gain of 10 dB, 1 dB compression point of 1 dBm, and power added efficiency of 20%. For both supply voltages, the input and the output of the circuit give good reflection performance. With this performance, the PA circuit may be used for low-power biomedical implanted transceiver systems.

Design of Highly Efficient Wideband RF Polar Transmitters Using the Envelope-Tracking Technique

This paper discusses the design issues of highly efficient and monolithic wideband RF polar transmitters, especially the ones that use the envelope-tracking (ET) technique. Besides first reviewing the current state-of-the-art polar transmitters in the literature, three focus topics will be discussed: 1) the system-on-a-chip (SoC) design considerations of the monolithic polar transmitter using ET versus EER (envelope elimination and restoration); 2) the design of highly efficient envelope amplifier capable of achieving the high efficiency, current, bandwidth, accuracy and noise specifications required for wideband signals; and 3) the design of high-efficiency monolithic Si-based class E power amplifiers (PAs) suitable for ET-based RF polar transmitters. A design prototype of a polar transmitter using ET and a monolithic SiGe PA that passed the stringent low-band EDGE (Enhanced Data rates for GSM Evolution) transmit mask with 45% overall transmitter system efficiency will be given; the simulated data of the entire polar transmitter system is also compared against the measurement. Further investigations on how to solve the technical challenges to successfully implement linear and high-efficiency ET-based polar transmitter for broadband wireless applications such as WiBro/WiMAX are also discussed.