SiGe-based Heterojunction Bipolar Transistor Research Articles

Design and analysis of the dynamic frequency divider using the BiCMOS–NDR chaos-based circuit

A dynamic frequency divider using a negative-differential-resistance (NDR) circuit combined with an inductor and a capacitor was demonstrated. This NDR circuit was made of Si-based metal-oxide-semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor devices. The operation of this frequency divider circuit was based on the long-period behavior of the nonlinear NDR circuit generating chaos phenomena. This circuit was analyzed by numerical simulation and the results showed that different dividing ratio could be obtained by modulating the input signal frequency using the MATLAB program and the HSPICE program. Some measured results were shown to verify our analyses. This application was designed based on a standard 0.18 μm BiCMOS technique.

Verification of theoretical model for collector current in SiGe‐based heterojunction bipolar transistors

The theoretical collector current model for SiGe-based heterojunction bipolar transistors under parallel–perpendicular kinetic energy coupling and anisotropic masses was validated. Verification was performed by comparison to Monte Carlo (MC) calculations and experimental data obtained from previous publications. Collector current against base-emitter voltage obtained by the present model is comparable to that calculated by the MC method. The measured collector currents as a function of base-collector voltage agreed well with the calculated currents for base-emitter voltages ranging from 0.3 to 0.6 V.

Design of NDR-Based Oscillators Suitable for the Nano-Based BiCMOS Technique

We present three oscillator designs using the negative-differential-resistance (NDR) circuit which is composed of several Si-based metal-oxide-semiconductor field-effect transistor (MOS) devices and one SiGe-based heterojunction bipolar transistor (HBT) devices. These oscillator circuits are composed of the NDR circuit, resistor, inductor, and capacitor. The oscillation frequencies are about several GHz based on the HSPICE simulation results. The circuits are designed using a standard 0.18 μm BiCMOS technique. Because our circuits are mainly made of a BiCMOS-NDR circuit that is different from a tradition NDR device made by a resonant tunneling diode with a quantum-well structure, we can utilize the nanobased BiCMOS process to implement these circuits by further improving the parameters.

Multiple-input logic circuit design using BiCMOS-based negative differential resistance circuits

We first propose an inverter circuit design using the negative differential resistance (NDR) circuit composed of the standard Si-based n-channel metal-oxide-semiconductor field-effect-transistor (NMOS) and SiGe-based heterojunction bipolar transistor (HBT). By suitably designing the MOS width/length parameters, we can obtain the ?-type NDR current---voltage (I---V) characteristic. Expanding the inverter circuit operation, the two-input and four-input NOR logic gates are demonstrated. Especially, the design and fabrication of the logic circuit is based on the standard SiGe BiCMOS process. Compared to the traditional NDR device like resonant tunneling diode (RTD), our MOS---HBT---NDR-based applications are much easier to be combined with some Si-based or SiGe-based devices on the same chip.

Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit

The monostable---bistable transition logic element (MOBILE) is a promising application for negative differential resistance (NDR) circuit. Previously reported MOBILE is constructed by resonant tunneling diode (RTD) that is implemented by the molecular beam epitaxy (MBE) process. However in this paper, we first propose a NDR circuit composed of standard Si-based metal---oxide---semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Then we demonstrate the inverter, NAND, and NOR gate operations using this MOS---HBT---NDR-based MOBILE circuit. The great advantage of this NDR-based application is that we can implement it using the standard SiGe BiCMOS process without the need for the MBE system.

Logic circuit design using monostable–bistable transition logic element based on standard BiCMOS process

We present a monostable–bistable transition logic element (MOBILE) based on the negative-differential-resistance (NDR) circuit. In particular, this circuit can be completely implemented using the standard BiCMOS process. A traditional MOBILE using two resonant tunneling diodes (RTD) connected in series is a functional logic circuit. The fabrication of RTD is utilized in the complicated molecular-beam-epitaxy (MBE) system. However, we present a MOBILE circuit that is completely made of standard Si-based metal-oxide-semiconductor field effect transistors and SiGe-based heterojunction bipolar transistors. By suitably determining the control voltages and input conditions, we can obtain the operation of the inverter, AND and OR logic gates. We also demonstrate the latch characteristic of this MOBILE circuit. This logic circuit is fabricated using the standard 0.35μm BiCMOS process without the need for the MBE system.

Voltage-controlled multiple-valued logic design using negative differential resistance devices

This paper demonstrates a concise and novel voltage-controlled multiple-valued logic (MVL) design using the standard BiCMOS technique. This MVL circuit is constructed by a voltage-controlled negative differential resistance (NDR) circuit, which is integrated by the standard Si-based metal–oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). There exists a two-peak current–voltage curve by connecting two integrated MOS–HBT–NDR elements in parallel as we suitably determine the width/length ( W/ L) of the MOS devices. In particular, each peak current can be effectively modulated by the corresponding controlled voltage. Using this special characteristic, we can obtain the three logic states with arbitrary sequence at the output.

Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit

A multiple-peak negative differential resistance (NDR) circuit made of standard Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) is demonstrated. We can obtain a three-peak I-V curve by connecting three cascoded MOS-HBT-NDR circuits by suitably designing the MOS parameters. This novel three-peak NDR circuit possesses the adjustable current-voltage characteristics and high peak-to-valley current ratio (PVCR). We can adjust the PVCR values to be as high as 11.5, 6.5, and 10.3 for three peaks, respectively. Because the NDR circuit is a very strong nonlinear element, we discuss the extrinsic hysteresis phenomena in this multiple-peak NDR circuit. The effect of series resistance on hysteresis phenomena is also investigated. Our design and fabrication of the NDR circuit is based on the standard 0.35 μm SiGe BiCMOS process.

Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources

The paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.

Design and characterization of the negative differential resistance circuits using the CMOS and BiCMOS process

We investigate four novel negative-differential-resistance (NDR) circuits using the combination of the standard Si-based n-channel metal-oxide-semiconductor field-effect-transistor (NMOS) and SiGe-based heterojunction bipolar transistor (HBT). By suitably designing the parameters, we can obtain the �- or N-type current---voltage (I---V) curve. Especially, the peak current of the combined I---V curve could be easy adjusted by the external voltage. In application, we utilize the NDR circuit to design an inverter circuit based on the monostable---bistable transition logic element. The fabrication of these NDR circuits and applications could be completely implemented by the simple and standard Si-based CMOS or SiGe-based BiCMOS process without using the complex and expensive process such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio

The paper demonstrates a novel two-peak negative differential resistance (NDR) circuit combining Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Compared to the resonant-tunneling diode, MOS-HBT-NDR has two major advantages in our circuit design. One is that the fabrication of this MOS-HBT-NDR-based application can be fully implemented by the standard BiCMOS process. Another is that the peak current can be effectively adjusted by the controlled voltage. The peak-to-valley current ratio is about 4136 and 9.4 at the first and second peak respectively. It is very useful for circuit designers to consider the NDR-based applications.

Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process

A novel multiple-selected and multiple-valued memory (MSMVM) design using the negative differential resistance (NDR) circuits is demonstrated. The NDR circuits are made of Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). During suitably designing the parameters and connecting three MOS---HBT---NDR circuits, we can obtain the three-peak current---voltage (I---V) curves with different peak currents in the combined I---V characteristics. For the traditional resonant-tunneling-diode (RTD) memory circuit, one can only obtain four-valued memory states using a constant current source to bias the three-peak NDR circuit. However in this paper, we utilize two switch-controlled current sources to bias the three-peak NDR circuit at different current levels. By controlling the switches on and off alternatively, we can obtain the four-valued, three-valued, two-valued, and one-valued memory levels under the four different conditions. Our design is based on the standard 0.35 μm SiGe BiCMOS process.

Design and fabrication of multiple-valued multiplexer using negative differential resistance circuits and standard SiGe process

The design of a four-valued multiplexer using the negative differential resistance (NDR) circuit is demonstrated. The NDR circuit used in this work is made of the Si-based metal–oxide–semiconductor field-effect-transistor (MOS) and the SiGe-based heterojunction bipolar transistor (HBT). However we can obtain the NDR characteristic in its combined I–V curve by suitably arranging the MOS parameters. This novel multiplexer is made of MOS–HBT–NDR-based decoders and inverters. The fabrication is based on the standard 0.35μm SiGe BiCMOS process.

Multiple-valued decoder using MOS-HBT-NDR circuit

The design of a four-valued decoder based on the negative-differential- resistance (NDR) circuit is demonstrated. The presented NDR circuit is composed of a Si-based metal-oxide-semiconductor field-effect- transistor (MOS) and a SiGe-based heterojunction bipolar transistor (HBT). The fabrication of the four-valued decoder using this MOS- HBT-NDR circuit is based on the standard 0.35 mum SiGe-based BiCMOS process.

The Influence of Selected Material and Transport Parameters on the Accuracy of Modeling Early Voltage in SiGe-Base HBT

Using a new model of Early voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> ), it is demonstrated that diffusion coefficient dependence on electric field and carrier velocity saturation at the collector end of the base has to be taken into account for accurate modeling of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> in SiGe-based heterojunction bipolar transistors. The need to incorporate the dependence of SiGe material parameters on the local Ge content in the base is also addressed

Characterization of neutral base recombination for SiGe HBTs

This paper, based on theoretical derivation of the expression for neutral base recombination (NBR) current, proposes a new characteristic parameter for NBR characterization and a method for estimating base minority-carrier lifetime for SiGe-base heterojunction bipolar transistors (HBTs). Furthermore, the proposed parameter is used to characterize the influence of NBR on the fabricated lightly base-doped SiGe and heavily base-doped SiGe:C HBTs. As a result, the base lifetimes are estimated to be around 2.0 and 0.10 ns for the SiGe and SiGe:C HBTs, respectively.

Effect of Ge content and profile in the SiGe base on the performance of a SiGe/Si heterojunction bipolar transistor

In this paper, the effects of Ge content and profile shape on the performance of a SiGe-based heterojunction bipolar transistor (HBT) are investigated. The common-emitter current gain, the early voltage, and the transit time of SiGe HBTs are calculated and computed for different Ge profiles as well as the total Ge content in the base, considering uniform base-doping. Then the effects of the above on the cutoff frequency fτ and the maximum oscillation frequency fmax of the HBT are shown. It is seen that both the forward current gain and the transit time decrease with the change in profile from box to triangle, but the early voltage increases with a similar change. The increase of Ge content for the same profile results in a decrease of transit time. From the analysis, a large increase in fτ and fmax can be predicted with a suitable choice of Ge profile and the total Ge content in the base. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 47: 247–254, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21138

Simulation analysis of the DC current gain in an n-p-n a-Si:H/SiGe/Si heterojunction bipolar transistor

This paper presents the results of a simulation study focused on the evaluation of the DC characteristics of an n-p-n SiGe-based heterojunction bipolar transistor (HBT) performing an extremely thin n+ hydrogenated amorphous silicon (a-Si:H) emitter. The a-Si:H(n)/SiGe(p) structure exhibits an energy gap difference of approximately 0.8eV mostly located at the valence band side and this results in an optimal configuration for the emitter/base junction to improve the emitter injection efficiency and thus the device performance.Considering a 20% Ge uniform concentration profile in the base region, simulations indicate that the DC characteristics of an a-Si:H/SiGe HBT are strictly dependent on two essential geometrical parameters, namely the emitter width and the base width. In particular, the emitter thickness degrades device characteristics in terms of current handling capabilities whereas higher current gains are obtained for progressively thinner base regions. A DC current gain exceeding 9000 can be predicted for an optimized device with a thin emitter and a 10nm-thick, 7×1018cm−3-doped base.

High‐speed self‐aligned SiGe HBT and application to optical‐fiber‐link ICs

AbstractSiGe base heterojunction bipolar transistor (HBT) has high‐frequency and high‐speed performance comparable to compound semiconductor devices, and also has high cost because the existing Si process is used. Hence, this HBT is expected to be a key device for high‐speed optical transmission systems and microwave/millimeter‐wave wireless systems. The self‐aligned SiGe HBT developed here has a PASS structure with selective epitaxial growth by UHV/CVD and buffered polycrystalline Si in the lower layer of the external base polycrystalline Si. In this way, high‐speed operation of the intrinsic transistor and reduction of the parasitic capacitance and resistance are realized at the same time. The cutoff frequency and maximum oscillation frequency of this SiGe HBT are 122 and 163 GHz, and the gate delay time of the ECL circuit is an extremely fast 5.5 ps. Further, an IC to form a 40 Gbit/s optical receiver is fabricated. A preamplifier with a 45‐GHz bandwidth, a limit amplifier with a gain of 32 dB, a frequency divider of 60‐GHz operations, and a 1:4 DEMUX with a decision circuit operating at 40 Gbit/s are realized. It is shown that the 40 Gbit/s optical receiver IC chip set with the present SiGe HBTs reached a practical level. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 85(7): 66–76, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10004

A high-power and high-gain X-band Si/SiGe/Si heterojunction bipolar transistor

A double mesa-type Si/SiGe/Si (n-p-n) heterojunction bipolar transistor (HBT) with record output power and power gain at X-band (8.4 GHz) is demonstrated. The device exhibits collector breakdown voltage BV/sub CBO/ of more than 24 V and a maximum oscillation frequency f/sub max/ of 37 GHz. Under continuous-wave operation and class-AB biasing conditions, 24.2-dBm (263-mW) RF output power with concurrent gain of 6.9 dB is measured at the peak power-added efficiency (28.1%) from a single ten-emitter fingers (780-/spl mu/m/sup 2/ emitter area) common-base HBT. The maximum RF output power achieved is as high as 26.3 dBm (430 mW in saturation) and the maximum collector efficiency is 36.9%. The low collector doping concentration together with the device layout result in negligible thermal effects across the transistor and greatly simplifies the large-signal modeling. The conventional Gummel-Poon model yields good agreement between the modeled and the measured de characteristics and small-signal S-parameters. The accuracy of the model is further validated with the measured power performance of the SiGe power HBT at X-band. These results set a benchmark for power performance for SiGe-based HBTs and indicate promise for their implementation in efficient X-band power-amplifier circuits.