Sidewall Spacer Research Articles

Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance

This study focuses on the design and analysis of Junctionless (JL) NSFETs, with an emphasis on the influence of spacer materials and temperature variations. A different number of materials such as Air, SiO2, Si3N4, HfO2, and TiO2 are examined for sidewall spacer compatibility in the JL-NSFET. The same materials are used for dual material spacers with combinations of: Air+HfO2, Air+TiO2, SiO2+HfO2, and SiO2+TiO2. The investigations revealed that the usage of TiO2 material gives better digital and analog performance with reduced leakage currents and subthreshold swing (SS), higher on/off ratio, voltage gain of ∼79.7 dB. Exploring the dual-k spacers produced better analog performance, gate control and reduced leakages for SiO2+TiO2 owing to the usage of higher dielectric material towards the gate. Further, the reduction of temperature from 400 K to 250 K for all the single-k and dual-k spacer materials revealed that the designed JL-NSFET is a suitable candidate at lower temperatures to improve the digital and analog performance whereas not recommended for RF performance improvement. Moreover, the SiO2+HfO2 spacer-based CMOS inverter is noticed to have better gain (∼15 V/V), noise margin, and lower delays (∼5.1 ps) when compared to TiO2 spacer-based complementary metal oxide semiconductor inverter making it suitable for digital IC applications.

Selective Epitaxial Growth of SiGe(:B) for Advanced p-Type Fd-SOI

We focus here on various Selective Epitaxial Growth (SEG) processes used during the manufacturing of advanced p-MOSFET devices: (i) 20 nm thick in-situ boron doped Si0.7Ge0.3 layers grown at 650 °C, 20 Torr then capped with 5 nm of Si:B (at 730 °C, 20 Torr) for Raised Sources and Drains (RSDs) and (ii) 8 nm intrinsic SiGe layers grown at 650–700 °C, 20 Torr for channels. Those layers were grown with a heavily chlorinated chemistry to maintain full selectivity versus SiN hard-mask or SiCO sidewall spacers. The impact of diborane, germane and hydrochloric acid mass-flows on growth kinetics and doping were first of all quantified on blanket wafers. Epitaxial processes were optimized in terms of (i) doping and growth rates, which should be as high as possible while still having superior structural and electrical properties and (ii) selectivity against dielectrics. In a second part, we highlight some of difficulties encountered when switching to patterned substrates. The morphology, faceting and loading effects in such layers are discussed.

Impact of eliminating ungated access regions on DC and thermal performance of GaN-based MIS-HEMT

The impacts of eliminating access regions (AR) on DC and thermal performance of GaN-based MIS-HEMT have been studied using a device of 4 µm gate length. Nominal absence of ARs was achieved by a metal-organic chemical vapor deposition-regrown heavily n-doped GaN contact region extended to the two-dimensional electron gas (2DEG) channel (with sheet resistance as low as 14 Ω/ ◻ and ohmic contact resistance of 0.20 Ω⋅ mm) and 22-nm-thick AlN/Al2O3/HfO2 insulator layers acting as both gate dielectrics and sidewall spacers. As a result, a low knee voltage (2.5 V @ VGS = +2 V) comparable to deeply-scaled devices was attained, revealing the dominant role of ARs in knee voltages. High linearity at lower supply voltages (gate voltage swing of 7.3 V @ VDS = 5 V) and a faster GVS saturation trend with V DS increasing were observed, benefiting from the improved utility of applied lateral voltage. Moreover, a much lower thermal resistance compared to that of the conventional MIS-HEMT structure (146 vs. 202 K W−1) was extracted by a static-pulsed I-V measurement method. Simplified TCAD simulations were conducted to explain the underlying mechanisms, demonstrating that the enhanced surface heat flow covered by the gate metal as well as the more uniform electric field along the 2DEG channel accounts for the better capability of heat management in the device free of ARs. Our results indicate the size of DC and thermal performance enhancements obtained by eliminating ARs in a GaN-based MIS-HEMT structure.

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

Thermal Atomic Layer Deposition of Silicon Carbonitride: A Density Functional Theory Study

Silicon carbonitride (SiCN) films have received considerable attention due to their lower dielectric constant and better etch selectivity than silicon nitride (SiN) films [1]. Therefore, SiCN is replacing SiN in a variety of applications, such as dielectric barriers for copper interconnects or sidewall spacers for self-aligned contacts. SiCN films have been mainly prepared by plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD). However, plasma-based deposition techniques suffer from poor film quality and lack of conformability on high-aspect-ratio patterns. Thermal atomic layer deposition at high process temperatures can deposit high-quality thin films with excellent conformality. However, no studies have been published on thermal ALD in SiCN, while there are a few reports on PEALD in SiCN. In this work, we studied the thermal ALD process of SiCN by alternating exposures to a carbon-containing silicon precursor and NH3 and compared it with the thermal ALD of SiN processes using carbon-free precursors. Density functional theory (DFT) calculations were used to model and simulate the continuous ligand exchange reactions between the silicon precursor and the substrate surface. The carbon incorporation in the growing film when using carbon-containing precursors was predicted by DFT, which is in good agreement with the experimental observations. Acknowledgments This work was supported by Hansol Chemical Co., Ltd.

Analytical modeling of negative capacitance transistor based ultra low power Schmitt trigger

Through an analytical framework, the work showcases the potential benefits of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) negative capacitance (NC) transistor (T) to enhance the hysteresis width (ΔVH) and reduce the minimum supply voltage (Vdd,min) of ultra low power (ULP) subthreshold Schmitt trigger (ST) at shorter gate lengths. Analyzing different ST configurations i.e. 2T (both NCFET), 4T-hybrid (realized through combination of NCFETs and MOSFETs), and 6T (all NCFETs or MOSFETs), leads to the inferences that (i) an inherent negative differential resistance of NCFET can be utilized for hysteresis in 2T-ST circuit, (ii) 4T-hybrid ST is not beneficial for enhancing ΔVH due to a current mismatch between MOSFET and NCFET, and (iii) an optimized 2T-ST and 6T-ST designed with high-permittivity (κ) sidewall spacer (Si3N4) and ferroelectric layer (6 nm) can function at Vdd,min of ∼ 55 mV, and ∼ 39 mV, respectively. Results indicate towards potential benefits of realizing ULP subthreshold ST through MFMIS NCFETs without any circuit overhead.

Demonstration of self-aligned β-Ga2O3 δ-doped MOSFETs with current density >550 mA/mm

We report on the design and fabrication of β-Ga2O3 self-aligned lateral MOSFETs by utilizing a heavily doped β-Ga2O3 cap layer. The fabrication of the self-aligned device used a combination of in situ Ga etching for damage free gate recess, in situ growth of Al2O3 for gate dielectric, and atomic layer deposited Al2O3 based sidewall spacers to form highly scaled (<100 nm) source–gate and gate–drain access regions. The fabricated device showed a record high DC drain current density of 560 mA/mm at a drain bias of 5 V. The DC current density was found to be limited by excessive self-heating resulting in premature current saturation in the device. Pulsed I–V measurements of the device showed a record high current density of 895 mA/mm and a high transconductance of 43 mS/mm, thanks to reduced self-heating in the device. The high current densities obtained in this work are promising for the development of high power density devices based on β-Ga2O3.

Improvement Breakdown Voltage by a Using Crown-Shaped Gate

In this paper, a crown-shaped trench gate formed by a sidewall spacer in insulated gate bipolar transistors (IGBT) is proposed to improve breakdown voltage. When a sidewall spacer is added to trench bottom corners, the electric field is distributed to the surface of the sidewall spacer and decreased to 48% peak value of the electric field. Thus, the sidewall spacer IGBT improved to 5% breakdown voltage. Another study proposed an additional oxide layer for trench bottom corners and improved breakdown voltage similar to the proposed IGBT. Previous studies have shown degradation in other electrical characteristics. However, this study shows a sidewall spacer IGBT that increases the current over 3% compared to a conventional trench IGBT when the applied gate voltage is under 4 V. Additionally, the turn-off loss characteristic is similar to conventional trench IGBT. Therefore, the breakdown voltage of the IGBT was improved while maintaining similar electrical properties to existing IGBTs through the crown-shaped gate.

Germanium Spherical Quantum-Dot Single-Hole Transistors With Self-Organized Tunnel Barriers and Self-Aligned Electrodes

We report the fabrication and electrical characterization of single-hole transistors (SHTs), in which a Ge spherical quantum dot (QD) weakly couples to self-aligned electrodes via self-organized tunnel barriers of Si3N4. A combination of lithographic patterning, sidewall spacers, and selfassembled growth was used for fabrication. The core experimental approach is based on the selective oxidation of poly-SiGe spacer islands located at the specially designed included-angle locations of Si3N4/Si-trenches. By adjusting processing times for conformal deposition, etch back and thermal oxidation, good tunability in the Ge QD size and its tunnel-barrier widths were controllably achieved. Each Ge QD is electrically addressable via self-aligned Si gate and reservoirs, thus offering an effective building block for implementing single-charge devices.

Impact of sidewall spacer materials and gate underlap length on negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET)

In this study, a negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET) with sidewall spacer engineering is proposed and its electrical characteristics are examined by technology computer-aided design (TCAD) simulation for lower subthreshold swing (SS) and higher on–off current ratio (Ion/Ioff) than conventional planar TFET. In detail, the dielectric constant (κ) and length of sidewall spacer (Lspc) which determine gate-to-source/drain underlap are optimized for an enhanced device performance. The simulation study shows that the sidewall spacers at source and drain underlap need to be designed differently for high Ion and low ambipolar current (Iamb). In case of source underlap, the HfO2 3 nm-Lspc can enhance outer fringing field and Ion. On the other hand, the SiO2 15 nm-Lspc at drain underlap can alleviate Iamb due to low outer fringing field. As a result, the asymmetric structure shows ∼ 1.5 times larger Ion and ∼ 4 orders lower Iamb with smaller SS and turn-on voltage (Von) than the conventional NCDG-TFET without sidewall spacer.

Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall Spacer in Negative Capacitance FinFET

Gate sidewall spacers, a pathway to the fringing fields, play a crucial role in the device design. In this article, using well-calibrated TCAD models, we have explored the impact of a sidewall ferroelectric (FE) spacer on a negative capacitance (NC) FinFET. In the proposed study, the FE layer is present beneath the gate electrode and at the spacer region that operates in the NC region. Through three novel FE–dielectric (FE–DE) spacer configurations, we found that proficient electrostatic control can be attained with the optimized stacked placement of the spacers. The fringing fields alter the FE polarization present at the spacer stack and modulates the channel charge, which is a prime objective of this work. Furthermore, we have varied the FE parameters, drain doping, and extension length to optimize the proposed FE–DE spacer configurations. We have done mixed-mode simulations to design an inverter and a three-stage ring oscillator to emphasize our results. The optimized spacer configuration shows~3.9% overshoot due to higher gate capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{GG}$ </tex-math></inline-formula> ); however, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ON}} / I_{\mathrm{OFF}}$ </tex-math></inline-formula> ratio is approximately twic than that of the baseline counterpart. The results reveal that the optimized spacer configuration also mitigates the negative differential resistance (NDR), which allows the NC-based devices to be an efficient candidate for analog applications.

Polycrystalline Silicon Nanowire Field Effect Transistor Biosensors for SARS-CoV-2 Detection

Disease detection and monitoring play a critical role in the ongoing COVID-19 pandemic. A comprehensive detection platform that enables early virus detection can effectively stem the spread of severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2). In this study, a polycrystalline silicon nanowire field-effect transistor (NWFET) was developed to detect the spike protein of SARS-CoV-2. The NWFET were fabricated through the application of sidewall spacer etching to maintain a nanowire diameter of less than 100 nm. The on–off current ratio of the transistor reached 106, and its subthreshold swing was 125 mV/decade, indicating the transistor’s strong attributes and stability. The biosensor based on this transistor reached a sensitivity of 59 mV pH−1 when used to test solutions with a pH value ranging between 6 and 9. We employed the biosensor in the detection of the SARS-CoV-2 spike protein, and the results revealed that the characteristic curve gradually shifted toward the left as the antigen of spike protein progressively increased in concentration. The limit of detection was estimated to be 0.51 ag ml−1. The results of the real-time testing of the spike protein were also successful, verifying the performance and applicability of the biosensor as a rapid screening tool for SARS-CoV-2.

Silicon Nanowires Length and Numbers Dependence on Sensitivity of the Field-Effect Transistor Sensor for Hepatitis B Virus Surface Antigen Detection.

Silicon nanowire field effect transistor (NWFET) sensors have been demonstrated to have high sensitivity, are label free, and offer specific detection. This study explored the effect of nanowire dimensions on sensors’ sensitivity. We used sidewall spacer etching to fabricate polycrystalline silicon NWFET sensors. This method does not require expensive nanoscale exposure systems and reduces fabrication costs. We designed transistor sensors with nanowires of various lengths and numbers. Hepatitis B surface antigen (HBsAg) was used as the sensing target to explore the relationships of nanowire length and number with biomolecule detection. The experimental results revealed that the sensor with a 3 µm nanowire exhibited high sensitivity in detecting low concentrations of HBsAg. However, the sensor reached saturation when the biomolecule concentration exceeded 800 fg/mL. Sensors with 1.6 and 5 µm nanowires exhibited favorable linear sensing ranges at concentrations from 800 ag/mL to 800 pg/mL. The results regarding the number of nanowires revealed that the use of few nanowires in transistor sensors increases sensitivity. The results demonstrate the effects of nanowire dimensions on the silicon NWFET biosensors.

Investigation of Gate Material Engineering in Junctionless Transistor for Digital and Analog Applications

In this paper, we propose dual material gate with dual-k dielectric gate oxide double gate junctionless transistor ‘DMG-DK-JLT’ for significant enhancement of performance. We showed, using 2D simulation that the proposed DMG-DK-JLT exhibit: 1) suppressed gate induced drain leakage due to band to band tunneling in OFF state (VDS = 1 V, VGS = 0 V) by 5 orders. 2) Impressively high ION/IOFF ratio of ~108. 3) For VGS=VDS = 1 V, DMG-DK-JLT performs better over conventional double gate JLT on various digital and analog performance metrics such as transconductance (Gm, 64% improvement), early voltage (VEA, 107% improvement), intrinsic gain (GmRO, 294% improvement), unity gain cutoff frequency (fT, 48% improvement), output resistance (Ro, 139% improvement), and transconductance-to-drain current ratio (Gm/ID, 218% improvement at VGS = 0.2 V, VDS = 1 V). We also compared its performance on above metrics with other gate material engineered Junctionless transistors. Moreover, we also show these values are further improved several orders by adding high-k gate sidewall spacer to our proposed DMG-DK-JLT.

Extended Total Mesorectal Excision Based on the Avascular Planes of the Retroperitoneum for Locally Advanced Rectal Cancer with Lateral Pelvic Sidewall Invasion.

It has been considered difficult to achieve en bloc resection in cases of locally advanced rectal cancer with lateral pelvic sidewall invasion. The present study demonstrates a novel surgical procedure for these tumors. There are 3 avascular planes of the retroperitoneum in the pelvic sidewall. Two visceral pelvic fasciae, namely the ureterohypogastric fascia and umbilical prevesical fascia, and the parietal pelvic fascia can be identified. In addition, the key structures of these fasciae, the ureter, umbilical artery, and external iliac vessels, can be identified transperitoneally before any dissection. Thus, these 3 avascular planes can be dissected without resorting to dissection of the retrorectal space. The key steps to this technique are: 1) after dissection from the side opposite to the site of tumor invasion to the dorsal side of the rectum, the avascular planes of the retroperitoneum among the 3 above-mentioned fasciae are dissected; and 2) the retrorectal space and pelvic sidewall space are connected by sharp dissection. Recognizing the 3 above-mentioned fasciae enables the dissection of the avascular planes of the pelvic sidewall, which helps to achieve en bloc dissection in cases of locally advanced rectal cancer with lateral pelvic sidewall invasion. The pelvic sidewall could be divided into 3 areas based on the visceral pelvic fasciae, which has helped to achieve en bloc dissection in cases of locally advanced rectal cancer with lateral pelvic sidewall invasion.

Analysis of gate-induced drain leakage in gate-all-around nanowire transistors

Gate-induced drain leakage (GIDL) is a serious problem in nanoscale transistors. In this paper, GIDL induced by longitude band-to-band tunneling (L-BTBT) in gate-all-around (GAA) nanowire transistors is investigated by 3D TCAD simulation. Effects of critical process parameters are analyzed, such as sidewall spacer characteristics, nanowire diameter, gate length and doping gradient in the source/drain extension region. The corner spacer and dual κ spacer are found to suppress L-BTBT current without degrading the dynamic performance. An underlap structure, a smaller nanowire diameter, and a gentle doping gradient at the source/drain extension are separately found as best choices, with regard to decreasing L-BTBT current. The underlying physical mechanisms are analyzed, and results indicate that increased L-BTBT width contributes to decreasing L-BTBT current. The results obtained here are reliable for optimizing the device structure, and help in low power circuit design based on nanoscale GAAFET.

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable low-power and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1–5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C OV) and 3% reduction in ring oscillator effective capacitance (C EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V BD) and leakage current (I LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.

Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure

In this article, structure optimization of high- ${k}$ interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High- ${k}$ IL can be formed during the high- ${k}$ gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high- ${k}$ IL ( ${T}_{\text {hk}}$ ) with gate length ( ${L}_{\text {G}}$ ), spacer length ( ${L}_{\text {ext}}$ ), and source/drain (S/D) length ( ${L}_{\text {S/D}}$ ), improved electrical performances were obtained. By optimizing ${T}_{\text {hk}}$ with properly adjusted ${L}_{\text {G}}$ , ${L}_{\text {ext}}$ , and ${L}_{\text {S/D}}$ , highly saturated ON-/OFF-current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay ( ${C}_{\text {gg}}$ ) properties and OFF-state leakage current were identified. In addition, the reason of increased OFF-state leakage, which can be shown when ${L}_{\text {ext}}$ shrinks with extending ${T}_{\text {hk}}$ , was also investigated. Finally, the optimized electrical characteristics were obtained when ${T}_{\text {hk}}$ is adjusted with ${L}_{\text {G}}$ and ${L}_{\text {S/D}}$ . The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when ${T}_{\text {hk}}$ is optimized through ${L}_{\text {G}}$ . On the contrary, reduced OFF-state leakage current and DIBL were confirmed in the case of optimization point with ${L}_{\text {S/D}}$ , which result in lower static power. Based on this comparison, optimization method and guideline for high- ${k}$ IL was proposed.

Trapping Depth and Transition Probability of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor

In this article, we investigate the four-level random telegraph noise (RTN) characteristics of a gate-all-around (GAA) nanowire (NW) transistor. The RTN-testing devices were fabricated with the sidewall spacer etching technique. The effective channel length and width are approximately 150 and 30 nm, respectively. By decoupling the four-level RTN, we are able to extract the time constants associated with the two traps. Circle-shaped approximations are used to mimic the triangular NW for evaluating the depths of the traps. The extracted depths of the two traps are very close to each other, which is consistent with the time-evolution measured results. We've also explored the probabilities of transitions between two specific current levels in the RTN characteristics, as well as the relative trapping/de-trapping frequencies.

Nitriding process for next-generation semiconductor devices by VHF (162 MHz) multi-tile push-pull plasma source

For the low power and high-performance semiconductor devices, a silicon oxynitride (SiOxNy) layer is required as the gate sidewall spacer material by replacing oxygen of the silicon oxide (SiO2) sidewall layer with nitrogen through a plasma nitriding process. In this study, as a plasma nitriding process, instead of conventional radio frequency plasma nitriding utilizing high frequency (HF; 13.56 MHz, etc.) plasmas, a very high frequency (VHF) plasma operated at 162 MHz with a multi-tile push-pull plasma source has been used in nitriding the SiO2 layer at room temperature and the effects of the VHF (162 MHz) plasma on SiOxNy formation from a SiO2 layer and electrical characteristics of the SiOxNy formed by the plasma nitridation were investigated. The use of the VHF (162 MHz) multi-tile push-pull plasma formed ∼10 nm thick SiOxNy with a very high nitrogen percentage of ∼24% on the SiO2 layer surface. Also, when the surface roughness of the SiOxNy and electrical characteristic of MOS capacitors fabricated with the SiOxNy formed by the VHF (162 MHz) plasma were compared with those formed by a capacitively coupled plasma at 60 MHz, a lower surface roughness and much lower leakage current of MOS capacitor could be obtained.