Sidewall Masked Isolation Research Articles

Modelling the sidewall masked oxidation process using the boundary element method

The two-dimensional thermal oxidation of silicon at moderate furnace temperatures has been modelled using a boundary element based algorithm, and an efficient computer code has been developed that provides a good representation of this complex moving boundary problem. The model is applied here to the optimisation of the sidewall masked isolation process, a technique that reduces the intrusion of the oxide beneath the nitride masking film and improves the packing density of the integrated circuits on the silicon wafer.

Structural and Electrical Characterization of SWAMI Techniques for Submicron Technologies

The SWAMI (side wall masked isolation) technique has been implemented in several VLSI and ULSI process outlines, as it is characterized by a low bird's beak extension, interesting topographical features such as a smooth top surface after field oxidation, and a low substrate defect density. In this work both the structural properties and electrical characteristics of single and double silicon etched SWAMI techniques are investigated. A comparison is also made with standard LOCOS isolation techniques. It will be demonstrated that the double silicon etch SWAMI structure is a very appropriate isolation alternative for standard LOCOS. The good electrical performance coupled with the geometry advantages, i.e., a high planarization level and a low bird's beak extension, make SWAMI a suitable isolation technique for future ULSI processing schemes.

Computer-aided design in VLSI device development

Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-masked isolation (SWAMI) for VLSI technology are then presented, followed by a discussion of the techniques used in the simulation of parasitic capacitances in multilayer interconnects for circuit performance evaluations.

Optimization of sidewall masked isolation process

This paper presents modifications of the Sidewall Masked Isolation (SWAMI) process for VLSI device isolation which improve process reproducibility, eliminate stress induced defects, and permit flexibility in channel stop implant optimization. A novel "undercut-and-backfill" technique is introduced to eliminate a localized failure mechanism of the oxidation mask by increasing the strength of the nitride-to-nitride joint. The primary variable influencing stress-induced defect generation is the vertical length of the sidewall nitride mask as determined by the amount of recessed silicon etch prior to sidewall nitride formation. In general, a maximum length can be found below which defect-free structures can be fabricated. An optional second recessed silicon etch, following the formation of the sidewall nitride, has been developed which increases the flexibility in optimizing the channel stop implantation. Defect-free low-leakage devices with near-zero electrical channel width reduction have been obtained.

Optimization of Sidewall Masked Isolation Process

This paper presents modifications of the Sidewall Masked Isolation (SWAMI) process for VLSI device isolation which improve process reproducibility, eliminate stress induced defects, and permit flexibility in channel stop implant optimization. A novel undercut-and-backfill technique is introduced to eliminate a localized failure mechanism of the oxidation mask by increasing the strength of the nitride-to-nitride joint. The primary variable influencing stress-induced defect generation is the vertical length of the sidewall nitride mask as determined by the amount of recessed silicon etch prior to sidewall nitride formation. In general, a maximum length can be found below which defect-free structures can be fabricated. An optional second recessed silicon etch, following the formation of the sidewall nitride, has been developed which increases the flexibility in optimizing the channel stop implantation. Defect-free low-Ieakage devices with near-zero electrical channel width reduction have been obtained.

0.5 μ SWAMI/NMOS process technology with electron beam lithography

This paper describes the process design and device characteristics of NMOS transistors with 0.5 μ mask layout in both channel width and channel length. Direct write electron beam lithography was used to fabricate submicron features. SWAMI (side wall masked isolation) and oxide spacer techniques were used to reduce both 2 Δ W and 2 Δ L to less than 0.3 μ with 6500 Å field oxide and 200 Å gate oxide. The device characteristics show that the threshold voltage of a 0.5 μ transistor is about 0.8 V, while the punch through and breakdown voltages are greater than 6.5 V. Short channel and narrow channel effects will also be presented.

IIB-5 improved sidewall masked isolation process

IIB-5 improved sidewall masked isolation process

The sloped-wall SWAMI—A defect-free zero bird's-beak local oxidation process for scaled VLSI technology

A new scheme for a Side WAll Masked Isolation (SWAMI) process is presented which takes all the advantages provided by LOCOS without suffering its difficulties. The new SWAMI technology incorporates a sloped silicon sidewall and a thin nitride layer around the island sidewalls such that both intrinsic nitride stress and volume expansion-induced stress are greatly reduced. A defect-free fully recessed zero bird's-beak local oxidation process can be realized by the sloped-wall SWAMI. Fabrication technology and NMOS electrical characteristics will be discussed. Two-dimensional simulation of total reduction in effective channel width for ideal vertical isolation, LOCOS, and SWAMI will also be presented. A SWAMI/CMOS circuit including 60K ROM, 2.5K SRAM, and 100 segments of display driver with 5.13 × 5.22 mm2chip size has been successfully fabricated. The results indicate that SWAMI is capable of replacing LOCOS as the isolation technology for submicrometer VLSI circuit fabrication.

A Bird's Beak Free Local Oxidation Technology Feasible for VLSI Circuits Fabrication

This paper presents a bird's beak free and fully recessed local oxidation-isolation structure employing only conventional LSI processing techniques; no additional masking step is required. A SideWAll Masked Isolation (SWAMI) process employing anisotropic plasma silicon etching and anisotropic plasma silicon nitride etching was implemented to form this new isolation structure. The SWAMI isolation scheme almost completely eliminates the reduction in effective channel width from drawn mask dimensions. The effective channel width obtained with the SWAMI isolation structure is independent of field-oxide thickness unlike the conventions LOCOS process. Fabrication technology and device characteristics of MOSFET's fabricated with the SWAMI isolation structure will be compared with the conventional LOCOS isolated MOSFET's.

A bird's beak free local oxidation technology feasible for VLSI circuits fabrication

This paper presents a bird's beak free and fully recessed local oxidation-isolation structure employing only conventional LSI processing techniques; no additional masking step is required. A SideWAll Masked Isolation (SWAMI) process employing anisotropic plasma silicon etching and anisotropic plasma silicon nitride etching was implemented to form this new isolation structure. The SWAMI isolation scheme almost completely eliminates the reduction in effective channel width from drawn mask dimensions. The effective channel width obtained with the SWAMI isolation structure is independent of field-oxide thickness unlike the-conventional LOCOS process. Fabrication technology and device characteristics of MOSFET's fabricated with the SWAMI isolation structure will be compared with the conventional LOCOS isolated MOSFET's.