0.5 μ SWAMI/NMOS process technology with electron beam lithography

Abstract

This paper describes the process design and device characteristics of NMOS transistors with 0.5 μ mask layout in both channel width and channel length. Direct write electron beam lithography was used to fabricate submicron features. SWAMI (side wall masked isolation) and oxide spacer techniques were used to reduce both 2 Δ W and 2 Δ L to less than 0.3 μ with 6500 Å field oxide and 200 Å gate oxide. The device characteristics show that the threshold voltage of a 0.5 μ transistor is about 0.8 V, while the punch through and breakdown voltages are greater than 6.5 V. Short channel and narrow channel effects will also be presented.