SiC Metal-oxide-semiconductor Field-effect Transistors Research Articles

Review and analysis of SiC MOSFETs’ ruggedness and reliability

SiC MOSFETs (silicon carbide metal-oxide semiconductor field-effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety-critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in-depth analysis. The ruggedness of SiC MOSFETs discussed here includes short-circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high-temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

Recent advances and trend of HEV/EV‐oriented power semiconductors – an overview

This study introduces the development advances and trend of power semiconductors used in hybrid and electric vehicles (HEV/EV). The status and forecast of power electronics’ requirement in HEV/EV are discussed along with a review of the automotive standard of power semiconductor devices. The advances in automotive semiconductor technologies such as Si-based insulated-gate bipolar transistor (IGBT) and freewheeling diode (FRD) and SiC-based metal oxide semiconductor field-effect transistor (MOSFET) and Schottky barrier diode are presented. The advances in automotive semiconductor packaging technologies are illustrated from three considerations, which are the low inductance in high-power density packaging, lower thermal resistance designing, and advanced packaging technologies. The challenges and development trend of more reliable power semiconductors for HEV/EV are discussed. The challenges in Si devices are focused on power density, efficiency, reliability, and packages, while the high temperature and low inductances are the main challenges for SiC devices. Lastly, the development trend is discussed in terms of four aspects, the new generation Si IGBT for HEV/EV, such as recessed-emitter-trench, reverse-conduction-IGBT, and smart IGBT; next generation SiC MOSFET; new packaging technology and material, such as planar packaging.

Family of DTMRC‐based DC–DC converters with an RZP

This study presents a novel family of dual-transformer multi-resonant DC–DC converters (DTMRCs) with a resonant zero point (RZP). The limitations of the conventional LLC resonant converter and its fundamental harmonic approximation (FHA) method are firstly discussed. On this basis, a unique RZP is combined with the dual-transformer architecture. As a result, both of the output voltage regulation capability and the over-current protection feature are promoted. Then, an extended describing modelling method is presented to improve the calculative accuracy of the FHA method. Moreover, by means of the appropriate placement of all three resonant frequencies, the fundamental and the third-order harmonic components are employed to transmit active power to the load simultaneously. The zero-voltage soft-switching characteristic is acquired for all the primary-side switches. Meanwhile, the preferable zero-current soft-switching feature is obtained for diodes both at the turn-on and turn-off moments. Therefore, the switching losses are significantly reduced for the proposed converters. Finally, with the employed SiC metal–oxide–semiconductor field-effect transistors, a 500-W half-bridge DTMRC prototype is built as an example, based on the P-type multi-resonant network. The experimental results demonstrate the validity and correctness of the theoretical analyses.

Comprehensive and systematic design of metal/high-k gate stack for high-performance and highly reliable SiC power MOSFET

Aluminum-based high-permittivity (high-k) gate dielectrics and suitable metal electrodes were systematically designed for advanced SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs). Although electron injection into alumina (Al2O3) was significantly suppressed by nitrogen incorporation (aluminum oxynitride: AlON), gate leakage current under negative gate bias and hole trapping into the dielectrics were observed. Adding hafnium into the AlON (HfAlON) was investigated to overcome these drawbacks, and an atomic layer deposition-based method for HfAlON was developed in terms of permittivity, energy bandgap, and hole conduction under negative stressing conditions. Consequently, the reliability of metal/high-k gate stacks under both positive and negative bias temperature stresses was improved by using an optimized HfAlON gate dielectric in combination with a high work-function TiN gate electrode. Thanks to the higher permittivity of HfAlON, peak transconductance was successfully enhanced up to 3.4 times with an acceptable reliability margin in the state-of-the-art trench SiC MOSFETs by implementing a TiN/HfAlON gate stack.

High-mobility SiC MOSFET with low density of interface traps using high pressure microwave plasma oxidation**Project supported in part by the National Key Research and Development Program of China (Grant No. 2016YFB0100601), the National Natural Science Foundation of China (Grant Nos. 61674169 and 61974159), and the Support from a Grant-In-Aid from the Youth Innovation Promotion Association of the Chinese Academy of

The microwave plasma oxidation under the relatively high pressure (6 kPa) region is introduced into the fabrication process of SiO2/4H-SiC stack. By controlling the oxidation pressure, species, and temperature, the record low density of interface traps (∼ 4 × 1010 cm−2⋅eV−1@Ec − 0.2 eV) is demonstrated on SiO2/SiC stack formed by microwave plasma oxidation. And high quality SiO2 with very flat interface (0.27-nm root-mean-square roughness) is obtained. High performance SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) with peak field effect mobility of 44 cm−2 ⋅eV−1 is realized without additional treatment. These results show the potential of a high-pressure plasma oxidation step for improving the channel mobility in SiC MOSFETs.

Unfamiliar pillars

Researchers from Sichuan University, China, propose a new superjunction (SJ) structure designed to reduce the power loss of insulated-gate bipolar transistors (IGBTs). The new ‘carrier-storage-enhanced SJ IGBT’ has a 23% lower on-state voltage drop compared to a n-Si/p-Si SJ IGBT. IGBTs are important parts of power semiconductor devices, which themselves are core components of power electronic circuits. IGBTs provide fast and efficient switching and consist of four alternating layers, controlled by a metal-oxide-semiconductor (MOS) gate structure. The efficiency of power electronic systems is linked to 3 factors: fast switching, high breakdown voltage (VB) and the difference between the turn-off loss (Eoff) and the on-state voltage drop (VCE(sat)) of the power semiconductor device. Huang (centre) and colleagues in their lab space at Sichuan University. Schematic diagram of energy band and carriers transport in the proposed SJ IGBT. Tradeoffs for VB-VCE(sat) (a) and Eoff-VCE(sat) (b). IGBTs with SJ structures incorporate pillars of n- and p-type semiconductor material (known as ‘doped’ material). This allows the IGBT to be turned off quickly, which can increase the difference between Eoff and VCE(sat), thus improving the device efficiency. However, as the adage goes, “with great doping comes great charge imbalance”. VB is sensitive to charge imbalance and thus the improvement in efficiency gained from the incorporated pillars is curtailed somewhat by the breakdown voltage's sensitivity. Recent work by Huang and colleagues led to the development of a so-called ‘carrier-storage-enhanced (CSE) SJ’ in which the p-pillar is connected indirectly to the emitter contact in the SJ structure. This effectively lowers the VCE(sat) and also reduces the amount of doping required in the n- and p-pillars, leading to an excellent Eoff-VCE(sat) tradeoff. The VB is still sensitive to the charge imbalance, and that is where the research group turned their attention next. By changing the chemical makeup of the SJ structure, using n-Si and p-3C-SiC pillars instead of n-Si and p-Si pillars, Huang's group found that the charge-imbalance sensitivity of VB was reduced. In addition, the new SJ structure was found to reduce the amount of reverse-recovery behaviour, which is undesirable in these devices. Coupling of the CSE-SJ and an IGBT gives rise to the (somewhat verbose) CSE-SJ-IGBT, the simulation results of which are presented in this issue of Electronics Letters. The simulation results for this device are promising. VCE(sat) is around 20% lower whilst maintaining the same V­B and Eoff. This improvement has been attributed to the CSE-SJ. The n-Si/p-3C-SiC heterojunction forms a high hole barrier, which prevents hole collection by the p-3C-SiC pillar. Huang is keen to produce the device to see how experimental results stack up against the simulated ones presented. A successfully fabricated CSE-SJ-IGBT that produces the same results as the simulation has the potential to be highly useful in medium- and high-power applications. IGBT devices have dominated medium-power applications for some time. Recently, however, the rise of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) have begun eating into the market of IGBT devices. Companies are exploring the potential of IGBT devices and the work presented here could one day be an important piece in the jigsaw of the future. Huang believes that SiC IGBT devices could be very promising in high-power applications, once the manufacturing process matures. It will be interesting to see what experimental studies of the device presented in Huang's submission discover and how it could potentially affect the future of power semiconductor devices.

High-temperature characteristics of SiC module and 100 kW SiC AC-DC converter at a junction temperature of 180 °C

High-temperature, high-power converters have gained importance in industrial applications given their ability to operate in adverse environments, such as in petroleum exploration, multi-electric aircrafts, and electric vehicles. SiC metal- oxide-semiconductor field-effect transistor (MOSFET), a new, wide bandgap, high-temperature device, is the key component of these converters. In this study, the static and dynamic characteristics of the SiC MOSFET, half-bridge module, are investigated at the junction temperature of 180 °C. A simplified experimental method is then proposed pertaining to the power operation of the SiC module at 180 °C. This method is based on the use of a thermal resistance test platform and is proven convenient for the study of heat dissipation characteristics. The high-temperature characteristics of the module are verified based on the conducted experiments. Accordingly, a 100 kW high-temperature converter is built, and the test results show that the SiC converter can operate at a junction temperature of 180 °C in a stable manner in compliance with the requirements of high-temperature, high-power applications.

Effect of Irradiation with 15-MeV Protons on Low Frequency Noise in Power SiC MOSFETs

Low frequency noise is studied in 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) irradiated with 15-MeV protons. Irradiation is carried out at room temperature in the frequency range from 1 Hz to 50 kHz upon irradiation with doses Φ of 1012 to 6 × 1013 cm–2. The frequency dependence of the spectral noise density SI follows the law SI ∝ 1/f with good accuracy. A correlation between the saturation current of the output characteristic Id(Vd) and the low-frequency noise level is traced. At doses in the range 1012 cm–2 ≤ Φ ≤ 6 × 1013 cm–2, the saturation current varies within about 20%, whereas the noise level changes by two orders of magnitude. The results of noise spectroscopy are used to estimate the trap density in the gate oxide, Ntv. In unirradiated structures, Ntv ≈ 5.4 × 1018 cm–3 eV–1. At Φ = 6 × 1013 cm–2, Ntv increases to ~7.2 × 1019 cm–3 eV–1.

Measurement of Thermal Parameters of SiC MOSFET Module by Case Temperature

SiC-based wide bandgap semiconductor devices such as metal–oxide–semiconductor field-effect transistors (MOSFETs) are gradually replacing Si devices in industrial applications because of their excellent electrothermal properties. However, the reliability of these devices and the problem of the junction temperature estimation are concerns that are yet to be resolved for these applications. This article proposes a method to measure the Cauer-type RC thermal network parameters that consider the influence of degradation of the external cooling system using either two or four case temperature cooling curves. The proposed method simplifies the measurement not only of the junction temperature and the power loss but also of the thermal equilibrium condition and it is thus suitable for the application in a power converter. Experiments were performed to prove that the thermal network parameters obtained are both feasible and credible.

Solid-State Generation of High-Frequency Burst of Bipolar Pulses for Medical Applications

This paper describes the operation of a solid-state generator proposed to produce high-frequency bipolar high-voltage pulse bursts on resistive-type loads, intended for medical applications. The generator design is based on two independent solid-state unipolar positive Marx generators positioned back to back, where the load is placed between the outputs of the two generators. SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are used in order to allow high-frequency operation. A generator with two five-stage Marx generators is experimentally tested in order to deliver up to 5000-V/50-A bipolar pulses, with 500-ns–10- $\mu \text{s}$ pulse widths and 200-ns–10- $\mu \text{s}$ relaxation time between positive and negative pulses. The generator operates in the burst mode from 1 to 200 pulses, in excess of 500 kHz within the burst, which can have a repetition frequency up to 1 kHz limited by the input 1000-V/200-W power supply, with forced air cooling. Results, with resistive-type loads, for several single pulse and burst mode operations are presented and discussed.

Investigation of 1200 V SiC MOSFETs' Surge Reliability.

In this work, the surge reliability of 1200 V SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) from various manufactures has been investigated in the reverse conduction mode. The surge current tests have been carried out in the channel conduction and non-conduction modes. The experimental results show that the maximum surge currents that the devices can withstand are similar for both cases. It is found that short circuits occurred between the gate and the source in the failed devices. The characteristics of the body diode have also changed after the tests. By measuring the device characteristics after each surge current is applied, it can be concluded that the damages to the gate oxide layer and the body diode occurred only when the maximum surge current is applied. By decapping the failed devices and observing the cross section of the damaged cell, it is found that high temperature caused by excessive current flow through the devices during the surge tests is the main reason for the device failure. Finally, the TCAD simulation of the devices has been carried out to bring insight into the operation of the devices during the surge events.

Shaping SiC MOSFET Voltage and Current Transitions by Intelligent Control for Reduced EMI Generation

In power converters, the fast switching of the power conversion components results in rapid changes in voltage and current, which results in oscillations and high-level electromagnetic interference (EMI), so the power components become a source of internal electromagnetic interference. Taking SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) as an example, an intelligent control method to suppressing interference sources is proposed in this paper. The combination of open-loop and closed-loop methods can simultaneously reduce the electromagnetic interference generated by voltage and current. Firstly, this paper analyzes how to select a reference signal. The relationship between the time domain and the frequency domain of the noise signal is analyzed. The convolution of the trapezoidal signal and the Gaussian signal is selected as the reference signal, which is named S-shaped signal in this paper. The S-shaped signal has continuous infinitely conductive characteristics, so its spectrum has a large attenuation in the high frequency region. Secondly, a new topology is proposed. Based on the closed-loop gate control, a current control signal is added, which can simultaneously shape the output voltage and control the output current slope. Both the simulation results and the experimental results show that the output voltage can follow the reference signal, S-shaped signal, and the slope and overshoot of output current can be changed. Compared with classical gate driver method, the spectrum of output voltage and output current obtained by the method proposed in this paper has a large attenuation, in other words, the electromagnetic interference is significantly reduced.

Carrier transport properties in inversion layer of Si-face 4H–SiC MOSFET with nitrided oxide

We propose a method to evaluate the carrier transport properties in the inversion layer of 4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) experimentally. Our approach differs from conventional methods, which have adjusted the parameters in conventional mobility models. Intrinsic phonon-limited mobility (μphonon) in the SiC MOSFET was observed by suppressing the severe impact of Coulomb scattering on the SiC MOS inversion layer by lowering the acceptor concentration (NA) of the p-type well region to the order of 1014 cm−3. In this study, we investigated the carrier transport properties in the inversion layer of Si-face 4H–SiC MOSFETs with nitrided oxide. It is revealed that the μphonon of the SiC MOSFET is a quarter or less than the conventionally presumed values. Additionally, surface roughness scattering is found not to be the most dominant mobility-limiting factor even at high effective normal field (Eeff) for the SiC MOSFET. These results demonstrate that conventional understanding of carrier scattering in the SiC MOS inversion layer should be modified, especially in the high Eeff region.

Influence of displacement damage induced by neutron irradiation on effective carrier density in 4H-SiC SBDs and MOSFETs

In this study, the fission neutron source and Co-60 gamma rays were employed to investigate the radiation effects on the electrical characteristics of the 4H-SiC SBDs and metal-oxide-semiconductor field-effect transistors (MOSFETs). The results indicated that SiC MOSFETs are more susceptible to gamma-ray irradiation than SiC Schottky barrier diodes (SBDs) due to the ionizing-produced charges trapped in the gate insulator. Compared to the ionizing effects caused by gamma rays, the neutron-induced displacement damage is more significant, since the defects originating from neutron irradiation would disturb the effective carrier density in SiC and lead to undesirable electrical deterioration and permanent failure of the SiC SBDs and MOSFETs.

Modeling and Evaluation of Stacking Fault Expansion Velocity in Body Diodes of 3.3 kV SiC MOSFET

We evaluated the stacking fault (SF) expansion velocity by electrical characteristics and estimated the screening test condition, which is a stress test with current to eliminate 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) whose forward voltage would be degraded during bipolar operation. First, double-diffused MOSFETs were fabricated, and forward current stress tests were applied to the body diodes in SiC MOSFETs. Their electrical characteristics were measured before and after forward voltage degradation at several junction temperatures. Second, to clarify the SF expansion sequence from a basal plane dislocation in the SiC epitaxial layer, continuous irradiation by an Hg lamp and photoluminescence (PL) observation were executed. Then, we present a model to explain the characteristics of the forward voltage degradation by a combination of the results of electrical measurement and PL observation. The characteristics calculated by using the presented model were in good agreement with the measured ones. Finally, forward current stress tests were applied to the body diodes in SiC MOSFETs with various conditions, and the SF expansion velocity was evaluated by calculation. These results indicate that the SF expansion velocity increases with forward current density and junction temperature. The estimated activation energy for the SF expansion velocity in the direction is estimated to be 0.24 eV at a forward current density of 120 A/cm2.

Comprehensive Characterization of the 4H-SiC Planar and Trench Gate MOSFETs From Cryogenic to High Temperature

In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance ( ${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$ ) and threshold voltage ( ${V}_{\text {th}}$ ) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times ( ${T}_{r}$ and ${T}_{f}$ ) and the corresponding energy loss ( ${E}_{r}$ and ${E}_{f}$ ) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures.

Extended T-type Inverter

Abstract This paper presents a new concept for a power electronic converter - the extended T-type (eT) inverter, which is a combination of a three-phase inverter and a three-level direct current (dc)/dc converter. The novel converter shows better performance than a comparable system composed of two converters: a T-type inverter and a boost converter. At first, the three-level dc/dc converter is able to boost the input voltage but also affects the neutral point potential. The operation principles of the eT inverter are explained and a simulation study of the SiC-based 6 kVA system is presented in this paper. Presented results show a serious reduction of the DC-link capacitors and the input inductor. Furthermore, suitable SiC power semiconductor devices are selected and power losses are estimated using Saber software in reference to a comparative T-type inverter. According to the simulations, the 50 kHz/6 kVA inverter feed from the low voltage (250 V) shows <2.5% of power losses in the suggested SiC metal oxide-semiconductor field-effect transistors (MOSFETs) and Schottky diodes. Finally, a 6 kVA laboratory model was designed, built and tested. Conducted measurements show that despite low capacitance (2 × 30 μF/450 V), the neutral point potential is balanced, and the observed efficiency of the inverter is around 96%.

Marx Generator Prototype for Kicker Magnets Based on SiC MOSFETs

This paper describes the design strategy for a new Marx generator, based on SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), proposed for Kicker magnet applications. As a starting point, the possible replacement of a thyratron tube associated with an existing kicker system, at CERN, is considered. The specifications of the output pulse are: 40-kV, 3.2-kA, 3- $\mu \text{s}$ flat top duration, 30-ns rise- and fall-time, and 1-Hz repetition rate. A theoretical study for a Marx generator topology, using 50 stages, each 800-V stage comprising 24 SiC MOSFETs in parallel, each MOSFET conducting approximately 140-A pulses is considered. In addition, a four-stage prototype has been evaluated, with almost full current and 3 kV, based on the proposed design, in order to assess the technological advantages of such a system and limitations for the scale up. First tests using parallel SiC MOSFETs are described and results discussed in light of the proposed topology and the physical structure of the assembly.

Impact of Different Gate Biases on Irradiation and Annealing Responses of SiC MOSFETs

The irradiation and postirradiation annealing responses of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are investigated under the application of different positive gate biases. During irradiation, the threshold voltage of the SiC MOSFETs showed a negative shift under the application of a positive gate bias. However, a significant reduction in this shift was observed as the positive gate bias increased from 20 to 24 V. The postirradiation annealing of the irradiated SiC MOSFETs was performed under various positive gate biases over the range from 32 to 44 V. A rapid reduction in the number of oxide-trapped charges was observed. These results indicate that the degradation of the threshold voltage in irradiated devices can be inhibited by the application of a higher gate voltage, while the high positive gate bias annealing represents an efficient way to recover the threshold voltage shift in these devices.

Oscillation analysis and current peak reduction in paralleled SiC MOSFETs

Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.