SiC Bipolar Junction Transistors Research Articles

Design Criterion for SiC BJTs to Avoid ON-Characteristics Degradation Due to Base Spreading Resistance

It is empirically known that the ON-resistance (voltage) of the SiC bipolar junction transistors (BJTs) with a thin-base layer is prone to be larger than the resistance of a voltage-blocking collector layer. In this paper, we explain the mechanism of this degradation of ON-characteristics by focusing on a high base spreading resistance and a parasitic diode existing below the base contact. An equivalent circuit model of the SiC BJT was proposed, and SPICE simulation was performed.In addition, TCAD simulation confirmed the validity of the model well. Based on the model, a design criterion to avoid the unwanted increase of the ON-resistance is proposed.

High Gamma Ray Tolerance for 4H-SiC Bipolar Circuits

A high gamma radiation hardness of 4H-SiC circuits is performed. The OR NOR circuits are based on emitter coupled logic (ECL), using integrated bipolar NPN transistors. Gain degradation in individual bipolar junction transistors (BJT) is minimal up to a dose of 38 Mrad (SiO2), but for the dose of 332 Mrad (SiO2) a degradation of 52% is observed. The SiC BJTs show higher radiation hardness than existing Si-technology and high stability under temperature stress. It is proposed that the oxide charge-dominated recombination is the key base current recombination mechanism contributing to gain degradation. An improvement in the gain is seen after annealing at 400 °C for 1800 s due to the possible annealing of some of the oxide defects contributing to the oxide charge.

Transient collector modulation of 4H–SiC BJTs during switch-on process

Main physical features of the collector resistance modulation processes have been studied via a one-dimensional simulation for n+–p–n0–n+ 4H–SiC bipolar junction transistor. The motion dynamics of minority carriers (holes) across the n0 collector layer during the switch-on process is traced. It is demonstrated that the effective modulation of the collector resistance is only possible in the case of a rather fast transistor switch-on. A necessary condition for the fast switch-on is the large amplitude and short leading edge of the base current pulse.

Non-ideal effect in 4H–SiC bipolar junction transistor with double Gaussian-doped base**Project supported by the National Natural Science Foundation of China (Grant Nos. 60876061 and 61234006), the Natural Science Foundation of Shaanxi Province, China (Grant No. 2013JQ8012), and the Doctoral Fund of the Ministry of Education of China (Grant Nos. 20130203120017 and 20110203110010).

The non-ideal effect of 4H–SiC bipolar junction transistor (BJT) with a double Gaussian-doped base is characterized and simulated in this paper. By adding a specific interface model between SiC and SiO2, the simulation results are in good agreement with the experiment data. An obvious early effect is found from the output characteristic. As the temperature rises, the early voltage increases, while the current gain gradually decreases, which is totally different from the scenario of silicon BJT. With the same effective Gummel number in the base region, the double Gaussian-doped base structure can realize higher current gain than the single base BJT due to the built-in electric field, whereas the early effect will be more salient. Besides, the emitter current crowding effect is also analyzed. Due to the low sheet resistance in the first highly-doped base epilayer, the 4H–BJT with a double base has more uniform emitter current density across the base-emitter junction, leading to better thermal stability.

Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs

The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50-150 nm were deposited prior to the same annealing process in N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, ~60 % higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of ~200 at room temperature and >100 at 300 °C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains.

High, Low, and Zero Field Spin Dependent Recombination in 4H SiC Metal Oxide Semiconductor Field Effect and Bipolar Junction Transistors

Silicon carbide based transistors have great promise in high temperature and high power applications. In particular, the great promise of silicon carbide based metal oxide semiconductor field effect transistors (MOSFETs) has been somewhat limited by materials physics problems in the region near the silicon carbide-silicon dioxide interface. Materials physics problems in SiC bipolar junction transistors (BJTs) are also topics of current interest. Studies involving a combination of high, low, and zero field electrically detected magnetic resonance via spin dependent recombination provide a powerful approach for the understanding of SiC transistor materials physics problems. In this paper, we will review our group’s work on multi-field spin dependent recombination of 4H SiC based MOSFETs and BJTs. We emphasize the physical principles involved in the measurements in part because they could potentially be quite useful if they were to be applied to other wide band gap semiconductor device systems.

Modeling of High Performance 4H-SiC Emitter Coupled Logic Circuits

SiC, a wide band gap semiconductor, is capable of robust operation at temperatures well above 600°C. SiC bipolar transistors are well suited for applications at high temperatures as, unlike MOSFET, it does not have a critical gate oxide, and hence oxide reliability at high temperatures is not an issue. In this paper, the design of optimized emitter coupled logic technology circuits using 4H-SiC bipolar transistors is presented. The circuits work over a wide range of temperatures and power supply voltages at high speeds, demonstrating the potential of robust high speed ECL integrated circuits in SiC for small-scale logic applications.

Parallel-Operation of Discrete SiC BJTs in a 6-kW/250-kHz DC/DC Boost Converter

This paper describes issues related to parallel connection of SiC bipolar junction transistors (BJTs) in discrete packages. The devices are applied in a high-frequency dc/dc boost converter where the switching losses significantly exceed the conduction losses. The design and construction of the converter is discussed with special emphasis on successful parallel-operation of the discrete BJTs. All considerations are experimentally illustrated by a 6-kW, 250-kHz boost converter (300 V/600 V). A special solution for the base-drive unit, based on the dual-source driver concept, is also shown in this paper. The performance of this driver and the current sharing of the BJTs are both presented. The power losses and thermal performance of the parallel-connected transistors have been determined experimentally for different powers and switching frequencies. An efficiency of 98.23% (±0.02%) was measured using a calorimetric setup, while the maximum temperature difference among the four devices is 12 °C.

Transient processes in high-voltage silicon carbide bipolar-junction transistors

The specific features of transient processes in high-voltage silicon carbide bipolar-junction transistors are studied theoretically and experimentally. It is shown that, in good agreement with the experimental results, the switch-off from the active mode can be described in a wide temperature range by the simple analytical expression derived in the study. The process in which a transistor is switched on to pass into the active mode is well described by a simple exponential dependence. The time constant of the switch-on process is determined by the average value of the collector capacitance before and after switch-on. A numerical model is suggested, based on a simple and physically transparent equivalent circuit describing, in good agreement with the experiment, both the transient processes of switch-on and switch-off in a SiC bipolar junction transistor, in both the active and saturation modes.

Characterization of the Stability of Current Gain and Avalanche-Mode Operation of 4H-SiC BJTs

The stability of the electrical characteristics of SiC n-p-n bipolar junction transistors (BJTs) is investigated under long-term avalanche-mode, dc, and pulsed-current operation. There is absolutely no change in the blocking I-V characteristics after a 934-h repetitive avalanche stress test. Long-term operation of the base-emitter diode (open-collector mode) alone does not result in any degradation of the ON-state voltage drop V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> or current gain β. Long-term operation in common-emitter mode results in negligible V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> or β degradation, if the base plate is maintained at 25°C. A greater degradation of β results upon increasing the base-plate temperature. The same total electrical charge, if passed through the BJT as a pulsed current, instead of a dc current, results in smaller β reduction. It is also shown that the β degradation can be reversed by annealing at ≥200°C, suggesting the possibility of degradation-free operation of SiC BJTs, when operating in pulsed current mode at ≥200°C temperatures.

Fabrication and characterization of 4H—SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H—SiC bipolar junction transistor with a double base epilayer that is continuously grown. The measured dc common-emitter current gain is 16.8 at IC = 28.6 mA (JC = 183.4 A/cm2), and it increases with the collector current density increasing. The specific on-state resistance (Rsp−on) is 32.3 mΩ·cm2 and the open-base breakdown voltage reaches 410 V. The emitter N-type specific contact resistance and N+ emitter layer sheet resistance are 1.7×10−3 Ω·cm2 and 150 Ω/□, respectively.

Enhanced Current Gain (&gt;250) in 4H-SiC Bipolar Junction Transistors by a Deep-Level-Reduction Process

We demonstrate 4H-SiC bipolar junction transistors (BJTs) with an enhanced current gain over 250. High current gain was achieved by utilizing optimized device geometry as well as optimized surface passivation, continuous epitaxial growth of the emitter-base junction, combined with an intentional deep-level-reduction process based on thermal oxidation to improve the lifetime in p-SiC base. We achieved a maximum current gain (β) of 257 at room temperature and 127 at 250°C for 4H-SiC BJTs fabricated on the (0001)Si-face. The gain of 257 is twice as large as the previous record gain. We also demonstrate BJTs on the (000-1)C-face that showed the highest β of 439 among the SiC BJTs ever reported.

4H-SiC BJTs with epitaxial junction termination composite structure

The proposed novel structure can be applied to junction termination technology to fabricate 4H-SiC bipolar junction transistors (BJTs) by using epitaxial junction termination extension (JTE) to eliminate the curvature effect of the base-collector junction terminal. Furthermore, accurate p-type dopants such as floating field limiting rings (FFLRs) have been implanted in the different zones of an epitaxial JTE to achieve the different charge distribution at the terminal of the main junction and JTE to decrease the peak electric field of the surface. Compared with the conventional JTE and FFLRs, the novel device can achieve a higher breakdown voltage by 20% and 39% added without the loss of current gain. Moreover, the novel structure not only simplifies the production of conventional SiC BJTs terminal process but also avoids the lattice injury for many ion implantations to produce the complex multiple JTE and FFLRs.

4H-SiC BJTs With Record Current Gains of 257 on (0001) and 335 on ($ \hbox{000}\bar{\hbox{1}}$)

We demonstrate 4H-SiC bipolar junction transistors (BJTs) with record current gains. An improved current gain was achieved by utilizing optimized device geometry and continuous epitaxial growth of the emitter-base junction, combined with an intentional deep-level-reduction process based on thermal oxidation to improve the lifetime in p-SiC base. A current gain (β) of 257 was achieved for 4H-SiC BJTs fabricated on the (0001) Si face. A gain of 257 is twice as large as the previous record gain. We also demonstrate BJTs on the (0001] ) C face that showed the highest β of 335 among the SiC BJTs ever reported.

Bipolar Integrated Circuits in 4H-SiC

Due to its wide band gap, 4H-SiC is potentially capable of sustained operation at temperatures well above 600 °C, but current devices are limited to lower temperatures by the stability of the metallization and passivation layers. SiC bipolar transistors are capable of operation at temperatures above 300 °C, as they do not have an oxide layer under high electric field and hence do not suffer from oxide reliability issues. In this paper, we describe bipolar digital integrated circuits on semi-insulating 4H-SiC that operate over a wide range of supply voltage and temperature, demonstrating the potential of SiC for high-temperature small-scale integrated-circuit applications.

Improved Current Gain in 4H-SiC BJTs Passivated with Deposited Oxides Followed by Nitridation

We report the improvement of current gain in 4H-SiC bipolar junction transistors (BJTs) by using deposited oxides as a surface passivation layer. Various post-deposition annealing processes were investigated. We successfully demonstrated SiC BJTs with a high current gain (β) of 86 using deposited oxides annealed in NO. This is 70% higher current gain compared with that of BJTs with the same structure with conventional thermally-grown oxides.

Improvement of Current Gain in 4H-SiC BJTs by Surface Passivation With Deposited Oxides Nitrided in $\hbox{N}_{2}\hbox{O}$ or NO

We report the improvement of current gain in 4H-SiC bipolar junction transistors (BJTs) by utilizing deposited oxides as a surface passivation layer. Various post deposition annealing processes, including annealing ambient (N2, N2O, and NO) and annealing time, were investigated. We successfully demonstrate SiC BJTs with high current gains (β) of 73 and 102 using deposited oxides annealed in N2O and NO, respectively, whereas BJTs having conventional thermally grown oxides showed a current gain of 50.

Two-dimensional analysis of the interface state effect on current gain for a 4H–SiC bipolar junction transistor

This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H–SiC bipolar junction transistor (BJT). Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H–SiC BJT performance.

10 kV, 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC

4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.

Improvement of Current Gain with Etched Extrinsic Base Regions of Triple Ion Implanted SiC BJT

In this paper, we demonstrate triple ion implanted 4H-SiC bipolar junction transistor (BJT) with etched extrinsic base regions. At the result of etching extrinsic base regions by mask of contact metals, maximum common emitter current gain was improved from 0.7 to 1.6.