Si Trench Research Articles

Cluster-Assisted Mesoplasma Chemical Vapor Deposition for Fast Epitaxial Growth of SiGe/Si Heterostructures: A Molecular Dynamics Simulation Study.

Co-condensation of mixed SiGe nanoclusters and impingement of SiGe nanoclusters on a Si substrate were applied using molecular dynamics (MD) simulation in this study to mimic the fast epitaxial growth of SiGe/Si heterostructures under mesoplasma chemical vapor deposition (CVD) conditions. The condensation dynamics and properties of the SiGe nanoclusters during the simulations were investigated first, and then the impingement of transient SiGe nanoclusters on both Si smooth and trench substrate surfaces under varying conditions was studied theoretically. The results show that the mixed nanoclusters as precursors demonstrate potential for enhancing epitaxial SiGe film growth at a high growth rate, owing to their loosely bound atomic structures and high mobility on the substrate surface. By varying cluster sizes and substrate temperatures, this study also reveals that smaller clusters and higher substrate temperatures contribute to faster structural ordering and smoother surface morphologies. Furthermore, the formed layers display a consistent SiGe composition, closely aligning with nominal values, and the cluster-assisted deposition method achieves the epitaxial bridging of heterostructures during cluster impingement, highlighting its additional distinctive characteristics. The implications of this work make it clear that the mechanism of fast alloyed epitaxial film growth by cluster-assisted mesoplasma CVD is critical for extending it as a versatile platform for synthesizing various epitaxial films.

Construction of 3D Patterns Through Modified Electrochemical Replication and Transfer

AbstractAs the development of flexible electronics continuously progresses, so does the demand for fabricated 3D electrodes via patterning technology. Electrochemical replication and transfer (ERT) has emerged as an efficient patterning technique, which deposits materials of interest on a predefined template via electroplating and subsequently transfers them onto target substrates. ERT can pattern large‐area 2D electrodes on nontraditional substrates whilst maintaining adequate flexibility, stretchability, and complex surface structures. This study extends the capability of ERT from 2D into 3D patterning. Via the rational design of a 3D SiO2/Si template, in which conductive Si trenches or holes are patterned with insulating SiO2 banks, electroplating of materials only occurs in the exposed Si surfaces so that both continuous and isolated 3D patterns with high aspect ratios up to 4:1 are realized. 3D‐ERT offers a high‐throughput and low‐cost approach to fabricating high Figure of Merit (>30 000) flexible transparent electrodes. Also, the application of 3D‐ERT in constructing highly sensitive, and self‐powered pressure sensors is showcased.

Wafer-Scale Fabrication of 2D Nanostructures via Thermomechanical Nanomolding.

With shrinking dimensions in integrated circuits, sensors, and functional devices, there is a pressing need to develop nanofabrication techniques with simultaneous control of morphology, microstructure, and material composition over wafer length scales. Current techniques are largely unable to meet all these conditions, suffering from poor control of morphology and defect structure or requiring extensive optimization or post-processing to achieve desired nanostructures. Recently, thermomechanical nanomolding (TMNM) has been shown to yield single-crystalline, high aspect ratio nanowires of metals, alloys, and intermetallics over wafer-scale distances. Here, TMNM is extended for wafer-scale fabrication of 2D nanostructures. Using In, Al, and Cu, nanomold nanoribbons with widths < 50nm, depths ≈0.5-1µm and lengths ≈7mm into Si trenches at conditions compatible is successfully with back end of line processing . Through SEM cross-section imaging and 4D-STEM grain orientation maps, it is shown that the grain size of the bulk feedstock is transferred to the nanomolded structures up to and including single crystal Cu. Based on the retained microstructures of molded 2D Cu, the deformation mechanism during molding for 2D TMNM is discussed.

Bias-supply timing tailored to the aspect ratio dependence of silicon trench etching in Ar plasma with alternately injected C4F8 and SF6

In semiconductor device fabrication, the feature profiles of a high-aspect-ratio (HAR) Si trench is needed to be controlled considering aspect-ratio-dependent etching (ARDE). This is achieved by a cyclic process in which Ar plasma is sustained while C4F8 and SF6 are alternately injected and a short-period supply of a substrate bias is provided. Presently, the transient behaviors of gaseous and surface reactions are dynamically revealed by measuring the plasma parameters using a surface wave probe and optical emission spectroscopy. When the etched surface is fluorinated during the cycle, an ARDE-free Si-trench feature profile can be fabricated by controlling the bias-supply timing.

Asynchronously Pulsed Plasma for High Aspect Ratio Nanoscale Si Trench Etch Process

The fabrication of high aspect ratio Si trenches has been becoming difficult due to the decrease in critical dimension (CD) to deep nanoscale. Especially, aspect ratio dependent etching (ARDE), which decreases the etch rate as the pattern width gets smaller, makes process uniformity get worse. In this study, the effects of bias pulsing parameters during asynchronous pulsing, which alternatively applies the source power and bias power, as well as the effect of additive gas such as CF4 and C4F8 on the nanoscale Si trench etch characteristics during Cl2/Ar plasma etching were investigated. It was found that the bias pulsing parameters during the asynchronous pulsing, such as bias pulse duty ratio and bias pulse delay time, can affect the etch characteristics such as etch rate, etch selectivity, and ARDE by changing the ion dose and ion energy during the etching. However, the variation of bias pulse parameters during the asynchronous pulsing did not change the etch profile noticeably, and it showed bowed Si trench etch profiles. To improve the etch profile, the addition of fluorocarbon gas such as CF4 and C4F8 was required, and by using C4F8 instead of CF4, more anisotropic Si etch profile without sidewall bowing could be obtained due to the improved sidewall passivation by a fluorocarbon layer even though it degraded etch selectivity and ARDE. Therefore, it is believed that by controlling the bias pulsing parameters with additive gas, nanoscale Si trench etch characteristics can be more easily controlled.

Strain Engineering in Si Split-Gate Trench Power MOSFETs by Partial Oxidation of Polysilicon Electrodes

Performance improvement of Si split-gate trench power MOSFETs due to conventional scaling is approaching a physical and economical limit. Strain engineering, however, enables enhanced device characteristics without the need for further shrinkage as a result of an increased charge carrier mobility in monocrystalline Si. In this work, thermally grown SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathbf {2}}$ </tex-math></inline-formula> functional strain layers are introduced into a state-of-the-art Si trench power MOSFET by partial oxidation of the source and gate electrode. The influence of the additional SiO2 layers on the strain distribution in monocrystalline Si is described by the thermomechanical (TM) strain simulation and the resulting device properties are assessed by means of detailed electrical analysis. For the strain-modified devices, the simulation shows higher longitudinal tensile strains in the direction of current flow and stronger out-of-plane compressive strains perpendicular to it, which have a beneficial effect on the electron mobility. The electrical characterization revealed improved ON-state resistances at gate voltages of 4.5 V ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}4.5$ </tex-math></inline-formula> ) and 10 V ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}10$ </tex-math></inline-formula> ) of up to 16.8% and 13.8%, respectively, while the breakdown voltage did not change. In the presence of the SiO2 layer in the gate electrode, the threshold voltage was reduced, which also contributed to the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}$ </tex-math></inline-formula> improvement. The functional strain layer in the gate electrode mainly influences the mobility in the channel, while it primarily alters the mobility in the drift region when introduced into the source electrode. However, the modification of mechanical strain in the channel area shows less impact on the overall device performance compared to the drift region.

Close-packed silicon field emitter arrays with integrated anode fabricated by electron-beam lithography

Design, fabrication, and characterization of close-packed field emitter tips enclosed in an Si trench and stand-alone arrays are presented. The two types of field emitter arrays (FEAs) are fabricated using a combination of high-throughput electron-beam lithography, plasma etching, and anode bonding integration technology. The field emitter array inside the trench shows a higher turn-on voltage compared to the stand-alone array. Without any tip sharpening, a current of 7.5 μA was observed at 300 V from FEAs inside the trench, while a higher current of 12.5 μA was observed at the same voltage for the stand-alone array.

Study on the Transformation of Si Trench Profile With Low Pressure of SF₆/O₂ Containing Plasmas

The reason for the change of trench sidewall profile under low pressure of SF6/O2 containing plasma was explored by studying the trench morphology under different etching conditions. The result shows that the Si undercut decreases with the decreasing of pressure and the uniformity will become better. However, the sidewall of the trench presents a negatively tapered under low pressure. The reasons for different profile of trench are explored by the thickness of sidewall protective layer for the first time. The TEM results show that the trench sidewall forms a protective film with a thickness of about 100Å. The thickness of the oxide layer decreases from top to bottom. And the EDX results show that the main elements of the protective film are Si and O. Due to the decrease of oxide thickness, the width of trench bottom will become larger and larger, resulting in negatively tapered morphology. It is worth noting that the profile of trench changes to positively tapered again under the condition of low ratio of SF6/O2. Based on this, an optimized trench etching process is proposed and the etch rate is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.15{\mu }\text{m}$ </tex-math></inline-formula> /min and the selectivity to the oxide mask is 14.

Adhesion Strength of Amorphous Carbon Films Deposited on a Trench Sidewall

Hydrogenated amorphous carbon (a-C:H) films were deposited on the sidewall of 3-mm-wide stainless steel or Si trench, and the adhesion strength of the films was evaluated using a micro-scratch tester. Particularly, the effects of carbon ion implantation and Si-containing interlayer (a-SiCx:H) as the pretreatments on the adhesion strength of the a-C:H films prepared on the trench sidewall were investigated. It was found that both carbon ion implantation and interlayer improved the adhesion strength of the a-C:H films deposited on the trench sidewalls. In addition, the carbon ion implantation dominated the adhesion strength of the a-C:H films for the Si substrates, and the interlayer for the stainless steel substrates. In the case of the stainless steel substrates, the carbon was accumulated on the surface of the trench sidewall instead of implantation, whereas the carbon ions were implanted to the Si substrates on the trench sidewall to form a mixing layer. The a-SiCx:H interlayer forms Fe–Si bonds between the stainless steel substrate and the interlayer, which is thought to improve the adhesion strength. It was also found that there is a negative correlation between the trench depth and the adhesion strength regardless of the pretreatment methods.

Synthesis of ultrathin heteroepitaxial 3C-SiC films by pyrolysis of molecular layer deposition polyamide films on Si

Polyamide films were grown on Si(111) using a molecular layer deposition (MLD) process with 1,2-ethylenediamine and trimesoyl chloride precursors at 120 °C. Synthesized polyamide films on Si(111) were then pyrolyzed in vacuum (10−7 Torr) to yield crystalline SiC thin films. High-resolution transmission electron microscope images of heat-treated samples showed the heteroepitaxial nature of the synthesized 3C-SiC (β-SiC) with respect to the Si(111) substrate. Raman, x-ray photoelectron spectroscopy, and x-ray diffraction analysis confirmed the formation of single-crystal SiC films. Samples pyrolyzed at 1300 °C showed defects attributed to Si sublimation. Formation of highly conformal SiC film after pyrolysis was demonstrated using Bosch-processed Si trenches. The thicknesses of 3C-SiC films obtained after pyrolysis were linearly dependent on the number of MLD cycles used to deposit polyamide films.

Molecular dynamics simulation of Si trench etching with SiO2 hard masks

Molecular dynamics simulations were performed to demonstrate nanometer-scale silicon (Si) trench etching with silicon dioxide (SiO2) hard masks by chlorine (Cl+) ion beams possibly with low-energy chlorine (Cl) radicals. Although the sputtering yield of SiO2 is typically much lower than that of Si, the etch rates of SiO2 and Si can be comparable because of the lower Si atomic density of SiO2. This implies that the erosion of the mask can significantly affect etched structures. This study has demonstrated that although the fluxes of incident ions and radicals are uniform in space and constant in time, the individuality of incident ions and radicals causes atomic-scale surface roughness, which cannot be neglected for nanometer-scale etched structures. Furthermore, some transient effects of surface etching, such as initial swelling of the Si surface due to incorporation of Cl atoms and preferential sputtering of oxygen, can affect the profiles of etched structures. The insufficiency of the local mechanical strengths of nanometer-scale materials also enhances their erosion, leading to the formation of nanometer-scale roughness on the sidewalls of masks and etched structures.

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

(Invited) Evaluation of Chemical and Physical Conformality for SiN x Films Deposited on Trench Substrate By Atomic Layer Deposition

I. Introduction State-of-the-art large-scale integrated circuit (LSI) requires three-dimensional complicated structures to further increase its packing density. High aspect ratio (AR), i.e. depth over opening, trench is one of the components to realize such kind of structure [1]. The trench surface often needs to be covered by insulator film, which is desired to have excellent conformality both in the physical and chemical viewpoints. The atomic layer deposition (ALD) is one of techniques suitable for such a requirement [2,3]. The ALD film theoretically consist of the same composition with the same thickness along the trench no matter how the AR is high, namely perfect conformality. In this study, we evaluated the ALD SiN x films along the trench with AR of 3 and 7.5. II. Experimen We deposited 10 nm-thick SiN x films using alternate supply of SiH2Cl2 and plasma enhanced NH3 precursors on the plane and trench structure with 40 nm opening and 120 or 300 nm deep, AR of 3 and 7.5 at 350, 550 and 630oC, respectively. The fabricated samples were evaluated using hard X-ray photoelectron spectroscopy (HAXPES), Fourier transform infrared spectroscopy (FT-IR) and transmission electron microscope (TEM) with energy dispersive X-ray spectroscopy (EDX). For the HAXPES evaluation, we carried out angle-resolved spectroscopy.Figure 1 shows a schematic diagram of angle-resolved HAXPES in the trench sample. Since the detection area changes with take-off angle (TOA), the SiN x film at the trench top is mainly evaluated at TOA 90. On the other hand, when the TOA is 75 or 60, the SiN x film on the trench sidewall is also evaluated.As the HAXPES equipment, a laboratory-based HAXPES (Lab. HAXPES) produced by ScientaOmicron Inc. was used [4]. The X-ray source energy was 9,251.74 eV from liquid GaKa. The photoelectron energy resolution was approximately 0.5 eV. III. Results and Discussion Figure 2 shows the EDX mapping of Si, O, and N atoms in AR7.5 sample deposited at 350oC. From Fig. 2 (a), nitrogen atoms are conformality distributed along the Si trench substrate. And Fig. 2 (b) shows that there is a large amount of oxygen atoms on the surface of the SiN x film at the trench sidewall. These results suggests that the oxygen atoms in the air may have bonded to nitrogen deficient bonds in the SiN x film formed on the trench sidewall. Figure 3 shows the Si 1s spectra from the AR7.5 trench sample deposited at 350oC using the angle-resolved HAXPES and the chemical shifts calculated from the Si 1s spectra. From Fig. 3 (a), the 1838.6 eV peak is assigned to the Si-Si bond of the Si substrate, and the peak around 1842 eV is assigned to Si-N bonds. The vertical axis in Fig. 3 (b) is the chemical shifts from the Si-Si bonds detected in the Si substrate. In other words, smaller shift indicates that the SiN x film has a non-stoichiometric characteristic with more N deficiencies. As shown in Fig. 3, the chemical shifts became smaller as the TOA decreased. Since the detection area of angle-resolved HAXPES with TOA75 and 60 is the top and sidewall of the trench structure, we consider that the photoelectrons originating from the nitrogen deficiency dominated from the trench sidewall. These results can be explained by the energy-loss of the plasma activated precursor in the trench structure while ALD process. We consider that the deactivation of the precursor prevented the formation of stoichiometric SiN x film on the trench sidewall, and that the N-deficient area was bonded by oxygen after exposure to the atmosphere. The stoichiometry uniformity was achieved by elevating the deposition temperature up to 550oC. IV. Conclusion In conclusion, we have evaluated the ALD SiN x film in the trench structure and found there were possible non-uniformity in the chemical structure along the trench although physically formed with excellent conformality. Acknowledgements We appreciate the SPring-8 BENTEN database for the Si 1s spectra assignment. Reference [1] T. Franza et al., ACS Appl. Mater. Interfaces 9, 1858 (2017).[2] T. Antonio et al., Materials Matters 13, 55 (2018).[3] X. Meng et al., Materials 9, 1007 (2016).[4] A. Regoutz et al., Rev. Sci. Instrum. 89, 073105 (2018). Figure 1

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual Fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual Fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

Etching of smoothing/without undercutting deep trench in silicon with SF6/O2 containing plasmas

In this article, the effects of He and Ar which are added into SF6/O2 containing plasmas were investigated in deep Si etching. External controllable parameters such as the He or Ar gas flow were used to study the changes of Si etch rate, Si undercut, oxide selectivity and feature shape correlation. The opening width of feature shape is from 0.22 μm to 0.42 μm. The result shows that the Si undercut decreases and the profile of Si trench is more vertical with the increasing He gas flow in all structures. But the Si etch rate and oxide selectivity will decrease. It is noteworthy that Ar and He have similar effects in reducing undercut. After detailed data analysis, it was found that there were some correlations between Si undercut and normalized residence time in both plasmas. The mechanism of this phenomenon is that the F radicals are diluted due to the addition of a large amount of He and Ar. With the decrease of the F radicals, the lateral etching ability decreases and undercut decreases. The concentration of O and F radicals decreases at almost the same rate when He or Ar gas is mixed, the sidewall profile of trench has no change. Due to the additional vertical bombardment of He+ and Ar+ which produces in the plasma with the addition of the He and Ar, the sidewalls of the Si trench become more vertical. Based on this, an optimized trench etching process is proposed and the etch rate is 1.25 um min−1, the selectivity for oxide mask is 9.5, and the undercut is less than 50 nm.

A Global Shutter Wide Dynamic Range Soft X-Ray CMOS Image Sensor With Backside- Illuminated Pinned Photodiode, Two-Stage Lateral Overflow Integration Capacitor, and Voltage Domain Memory Bank

This article presents a prototype $22.4~\mu \text{m}$ pixel pitch global shutter (GS) wide dynamic range (WDR) soft X-ray CMOS image sensor (sxCMOS). Backside-illuminated (BSI) pinned photodiodes with a 45- $\mu \text{m}$ thick Si substrate were introduced for low noise and high radiation hardness to high energy photons. Two-stage lateral overflow integration capacitor (LOFIC) and voltage domain memory bank with high-density Si trench capacitors were introduced for WDR and for GS. The developed sxCMOS achieved maximum 21.9 Me− full well capacity with a single exposure 129 dB dynamic range by GS operation. Over 70% quantum efficiency (QE) toward soft X-ray was successfully achieved. The developed prototype sxCMOS is a step forward toward a 4 M pixel detector system to be utilized in next-generation synchrotron radiation facilities and X-ray free-electron lasers.

Reliable endpoint technique on Si trenching for backside circuit edit

Circuit Edit (CE) techniques have been used for debug, characterization and prototyping. in the IC industry. CE jobs have become more complex to accomplish since the adaption of FinFET technology. Backside Si trenching as part of CE process is required to have the highest success rate because once punched through Si trench floor, the IC would lose functionality. Therefore, it needs reliable and quantitative end-pointing technique. The coaxial FIB column technology [1] allows to obtain optical image simultaneously, so the optical interference fringes can be used to estimate remaining of Si thickness, to monitor planarity of trench floor and to obtain trenching endpoint. We introduce reliable end-pointing technique on backside Si trenching.

InAs nano-ridges and thin films grown on (001) silicon substrates

Monolithic integration of InAs related devices on (001) Si platforms offers potential to extend integrated Si photonics to the mid-infrared (MIR). Here, we systematically studied the hetero-epitaxial growth of in-plane InAs nano-ridges and coalesced thin films on CMOS-standard (001) Si wafers. We started with the growth and optimization of in-plane InAs nano-ridges inside nano-scale Si trenches and developed a three-step growth procedure with a reduced growth rate to obtain uniform InAs nano-ridges with excellent crystalline qualities. We then developed a coalescence process for the optimized InAs nano-ridges to evolve into high quality continuous thin films. In the parametric growth study, we found that a low coalescence rate results in the formation of large InAs islands, while a high coalescence rate promotes the creation of uniform InAs thin films. These InAs/Si templates could serve as virtual substrates for the growth of light emitters and detectors in MIR Si photonics.

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

A feasibility study has been carried out to find an alternative method to the laborious cum expensive physical vapor deposition (PVD)/atomic layer deposition for the deposition of barrier and seed metal layers inside the deep Si trenches with aspect ratio (AR) greater than 10, by using low-cost, highly-scalable, CMOS-compatible electroless (EL) plating method to plate Ni as (barrier cum) seed layer for the fabrication of sub-μm as well as 10 μm width copper through-silicon-vias (Cu-TSVs). Micro-structural data revealed that both sub-μm and 10 μm width TSVs with AR ranging from 12 to 17 were completely filled with Cu by using EL-Ni as a seed layer. Further, both scanning electron microscope and energy dispersive X-ray analyzes data confirms the conformal formation of EL-Ni all through TSV sidewall and TSV bottom, which is otherwise difficult to realize by the even sophisticated PVD tool. Therefore, the EL plating method appears to be a highly promising method for the conformal formation of barrier/seed layers inside the high AR TSVs for future three-dimensional integration and packaging applications.

Over 100 Million Frames per Second 368 Frames Global Shutter Burst CMOS Image Sensor with Pixel-wise Trench Capacitor Memory Array.

In this paper, a prototype ultra-high speed global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with pixel-wise trench capacitor memory array achieving over 100 million frames per second (fps) with up to 368 record length by burst correlated double sampling (CDS) operation is presented. Over 100 Mfps high frame rate is obtained by reduction of pixel output load by the pixel-wise memory array architecture and introduction of the burst CDS operation which minimizes the pixel driving pulse transitions. Long record length is realized by high density analog memory integration with Si trench capacitors. A maximum 125 Mfps frame rate with up to 368 record length video capturing was confirmed under room temperature without any cooling system. The photoelectric conversion characteristics of the burst CDS operation were measured and compared with those of the conventional CDS operation.