Top Si Layer Research Articles

A new structure and its analytical breakdown model of high voltage SOI device with Step Unmovable Surface Charges of buried oxide layer

A new SOI (Silicon On Insulator) high voltage device with Step Unmovable Surface Charges (SUSC) of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson’s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF (REduce SURface Field) condition of the SOI device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3μm-thick top Si layer, 2μm-thick buried oxide layer and 70μm-length drift region using a linear doping profile of unmovable buried oxide charges.

X-Ray Reciprocal Space Mapping and Synchrotron Radiation Topography of Strained Si/Si1-xGex on Bonded SOI

In this work, X-ray triple-axis diffractometry (TAD) and synchrotron radiation double-crystal topography (SRDT) have been utilized to investigate strained-Si/Si1-xGex on bonded SOI. The structural characteristics of the Si capping layer and the underlying Si layers (the Si buffer and SOI top Si layer) have been described using high resolution reciprocal lattice mapping (HRRLM). The mosaicity in the SiGe layer leads to (004) diffraction peak broadening asymmetrically. The crosshatched contrast spatially correlated with the misfit dislocations (MDs) has been observed both in the SiGe layer and the underlying Si layers. The granular pattern due to the mosaic blocks is also shown in the topograph of the SiGe layer. It is argued that the compressive strain in the SiGe layer has been primarily released at the interface between the SiGe layer and the underlying Si layers.

Fabrication of silicon-on-SiO2/diamondlike-carbon dual insulator using ion cutting and mitigation of self-heating effects

A diamondlike-carbon (DLC) layer was used to substitute for the buried SiO2 layer in silicon on insulator (SOI) to mitigate the self-heating effects in our previous study. However, we discovered drawbacks associated with the inferior Si/DLC interface, inadequate thermal stability as well as carbon-silicon interdiffusion at the Si/DLC interface that could hamper future application of this silicon-on-diamond structure to microelectronic devices. In this work, we introduced a silicon dioxide barrier layer between the Si film and DLC buried layer to form a silicon-on-SiO2∕DLC dual-insulator structure to tackle these problems. Cross-sectional high-resolution transmission electron microscopy reveals that the Si/insulator interface is atomically flat and the top Si layer has nearly perfect crystalline quality. The SiO2∕DLC dual-insulator layer retains excellent insulating properties at typical complementary metal oxide silicon processing temperatures. Numerical simulation reveals that the negative differential resistance and channel temperature are significantly reduced compared with those of the same metal oxide semiconductor field effect transistors fabricated in conventional SiO2-based SOI, suggesting that the silicon-on-dual-insulator structure can alleviate the self-heating penalty effectively.

Raman investigation of strain in Si∕SiGe heterostructures: Precise determination of the strain-shift coefficient of Si bands

Raman scattering experiments were carried out on Si∕SiGe heterostructures. The strain in both the top Si layer, and the Si1−xGex buffer layers with various Ge compositions was evaluated using several excitation sources, together with x-ray diffraction and secondary ion mass spectrometry. The strain-shift coefficient, which is a necessary quantity to evaluate the strain by Raman spectroscopy, was precisely determined. The dependence of the Si–Si band frequency on the Ge composition in the SiGe alloy was also examined. We found that the strained top-Si layers with a thickness below 25nm experience coherent growth on Si1−xGex buffer layers with composition x<0.35.

Investigation of Si/SiGe/Si on bonded silicon-on-insulator by triple-axis X-ray diffraction and synchrotron radiation double-crystal topography

Triple-axis X-ray diffraction (TAD) along with synchrotron radiation double-crystal topography (SRDT) is first time employed to investigate Si/SiGe/Si heterostructures on a bonded silicon-on-insulator (SOI) wafer. (0 0 4) TAD measurements present the crystallographic misalignment of the whole structure and the two diffraction peaks from the Si layers (i.e. the Si capping layer, the Si buffer and the SOI top Si layer) with the shift in Bragg angle. The bulk Si peak, the Si layers peak, and the SiGe layer peak on the SRDT (0 0 4) rocking curves are discerned, respectively. The asymmetry of the Si layers peak is attributed to the slight difference in lattice spacing and the little crystallographic misalignment. The two diffraction peaks with the shift in Bragg angle are identified from the Si capping layer and the underlying Si layers (i.e. the Si buffer and the SOI top Si layer). (0 0 4) symmetrical and (1 1 3) asymmetrical diffraction measurements demonstrate that the tensile strain and Ge diffusion result into the shift in Bragg angle of the Si layers.

Surface Inspection of Silicon-on-Insulator Wafers with Ultra Thin Top-Si Layer by Laser Scattering

This paper discusses an investigation into the abilities to detect light point defects on a silicon-on-insulator (SOI) wafer surface by inspecting both the haze and the scattering intensity of the poly styrene latex (PSL) spheres on a SOI wafer with a top-Si layer thinner than 120 nm. It is found that a SOI wafer with a top-Si layer thickness exhibiting a lower reflectance at the wavelength used in scanning the surface results in a higher haze and weaker scattering intensity for PSL spheres. Although each size of PSL spheres has its own thickness of its top-Si layer with its lowest scattering intensity. The electric field distributions above the SOI wafer surface with various top-Si thicknesses are calculated to evaluate the potential for scattering the incident light at various wavelengths by the surface particles. It is predicted that p-polarized light with wavelengths between 290 and 370 nm is most suitable for inspecting SOI wafers with a top-Si layer thickness below 120 nm.

Thermal stability of CoSi2 layers implemented in a silicon-on-insulator substrate

A silicon-on-metal-on-insulator substrate, consisting of a top Si layer, a buried CoSi2 layer and a buried SiO2 layer on a Si (1 0 0) substrate was formed using Co silicidation, wafer bonding and wafer splitting. It is shown that the buried silicide layers in this structure exhibit a much higher thermal stability than surface layers. Resistivity measurements and cross-sectional transmission electron microscopy investigations revealed that buried CoSi2 layers withstand furnace anneals at 1000 °C up to 2 h, while surface CoSi2 layers started to degrade after 10 min anneals at 1000 °C. The proposed substrate is most useful for BiCMOS applications.

Structural Characterization of Epitaxial Si / Pr<sub>2</sub>O<sub>3</sub> / Si(111) Heterostructures

The use of heteroepitaxial Si / Pr2O3 / Si(111) systems as semiconductor-insulatorsemiconductor (SIS) stacks in future applications requires a detailed structural characterization. We used X-ray reflectivity (XRR) to control layer thickness and interface roughness, standard X-ray diffraction (XRD) to analyze the Pr2O3 phase, orientation and crystal perfection, and grazing incidence XRD to study the thin epitaxial Si top layer. Transmission electron microscopy (TEM) was used to prove the results by direct imaging on a microscopic scale. Pr2O3 grows epitaxially in its hexagonal phase and (0001) orientation on Si(111) substrates. An epitaxial Si overgrowth in (111) orientation and good perfection is possible, but such Si layers exhibit two stacking twins, one with the same in-plane orientation as the substrate and one rotated by 180° around the Si [111] direction.

Transition from wire formation to island formation in thermal agglomeration of a (111) silicon-on-insulator layer

The effects of Si layer thickness on thermal agglomeration of a (111) bonded silicon-on-insulator (SOI) structure were studied. As starting material, (111) bonded SOI wafers with their top Si layer thinned to 2–9 nm were used. The samples were subjected to thermal treatment at 950 °C in ultrahigh vacuum. Atomic force microscopy revealed that, in the 4–9 nm thickness range, the top Si layer is deformed into wire arrays in the 〈112¯〉 directions. However, at thicknesses below 4 nm, randomly formed Si islands were observed. This structural transition from wires to islands is presumably due to the atomic-scale thickness fluctuation in the initial Si layer.

Local-strain effects in Si∕SiGe∕Si islands on oxide

The tensile-strained Si, based on the misfit between Si and SiGe gives high speed and high drive current to the metal-oxide-silicon field effect transistors. In order to achieve the total system minimum energy, the island edge, within some characteristic length, bends upwards giving rise to a distorted lattice, as simulated by the finite element method. The finding indicates that the conventional strain partition rule of Si∕SiGe∕Si layers used for a large island size (>10μm) is not adequate for a small island size (<200nm) due to the significant local-strain effect of the edge lattice distortion. For a small island size, the bending from the edge can significantly affect the strain on the surface of the top Si layer, and a compressive strain or reduced tensile strain occurs at the center of the top Si layer, while the conventional strain partition rule predicts a uniform tensile strain on the top Si layer for any size of Si∕SiGe∕Si islands.

Thermally-induced formation of Si wire array on an ultrathin (111) silicon-on-insulator substrate

We have found that a Si wire array is formed by thermal agglomeration of an ultrathin (111) Si layer in a bonded silicon-on-insulator (SOI) structure, although previous studies for crystalline and amorphous Si layers on SiO2 only showed island formation. As starting material, (111) bonded SOI wafers with the top Si layers thinned to 5–9 nm were used. The samples were then subjected to a thermal treatment at 950 °C in an ultrahigh vacuum. Atomic force microscopy revealed that the (111) top Si layer is deformed into three sets of wire arrays in the three equivalent ⟨112¯⟩ directions. It is also shown that the patterning of a Si layer leads to the wire array selectively formed in one of these three directions.

Plasma hydrogenation of strained Si∕SiGe∕Si heterostructure for layer transfer without ion implantation

We have developed an innovative approach without the use of ion implantation to transfer a high-quality thin Si layer for the fabrication of silicon-on-insulator wafers. The technique uses a buried strained SiGe layer, a few nanometers in thickness, to provide H trapping centers. In conjunction with H plasma hydrogenation, lift-off of the top Si layer can be realized with cleavage occurring at the depth of the strained SiGe layer. This technique avoids irradiation damage within the top Si layer that typically results from ion implantation used to create H trapping regions in the conventional ion-cut method. We explain the strain-facilitated layer transfer as being due to preferential vacancy aggregation within the strained layer and subsequent trapping of hydrogen, which lead to cracking in a well controlled manner.

Challenge to 200 mm 3C-SiC Wafers Using SOI

200 mm wafer with 3C-SiC/SiO2/Si structure has been fabricated using 200 mm siliconon- insulator (SOI) wafer. A top Si layer of 200 mm SOI wafer was thinned down to approximately 5 nm by sacrificial oxidization, and the ultrathin top Si layer was metamorphosed into a 3C-SiC seed layer using a carbonization process. Afterward, an epitaxial SiC layer was grown on the SiC seed layer with ultra-high vacuum chemical vapor deposition. A cross-section transmission electron microscope indicated that a 3C-SiC seed layer was formed directly on the buried oxide layer of 200 mm wafer. The epitaxial SiC layer with an average thickness of approximately 100 nm on the seed was recognized over the entire region of the wafer, although thickness uniformity of the epitaxial SiC layer was not as good as that of SiC seed layer. A transmission electron diffraction image of the epitaxial SiC layer showed a monocrystalline 3C-SiC(100) layer with good crystallinity. These results indicate that our method enables to realize 200 mm SiC wafers.

Range evaluation in SIMS depth profiles of Er-implantations in silicon

In the last decade ion implantation of common dopants in silicon has been almost full characterised. However, data of inner transition elements are based on few measurements or even extrapolations. Our investigations focus on erbium, an upcoming dopant in photonic applications. Some of us have previously found errors of 20% in the projected range of Er in Si and SiO 2 when comparing the range profiles measured with SIMS and simulations using SRIM, T2D, and our own binary collision simulator IMSIL. Because of the far-reaching consequences, we have performed additional, more precise experiments to confirm our previous results. Equal doses of Er has been implanted into SIMOX wafers with energies of 100, 200, 300, 400, 500, and 600 keV. Profiles have been measured with secondary ion mass spectrometry (SIMS). Relative sensitivity factors (RSF) were gathered from low-energy implantations, remaining within the Si top layer. We used the Si/SiO 2 interface at exactly 217.7 nm to calibrate the depth scale of all profiles. In addition dynamical Monte-Carlo simulations of the sputter process were taken to correct the depth scale and the interface position.

비정질 n형 Si 박막을 이용한 자기터널링 트랜지스터 제작과 특성

Magnetic tunneling transistor (MTT) device using the amorphous n-type Si semiconductor film for base and collector consisting of the [CoFe/NiFe](free layer) and Si(top layer) multilayers was used to study the spin-dependent hot electron magnetocurrent (MC) and tunneling magnetoresistance (TMR) at room temperature. A large MC of 40.2 % was observed at the emitter-base bias voltage ( ) of 0.62 V. The increasing emitter hot current and transfer ratio ( / ) as are mainly due to a rapid increase of the number of conduction band states in the Si collector. However, above the of 0.62 V, the rapid decrease of MC was observed in amorphous Si-based MTT because of hot electron spin-dependent elastic scattering across CoFe/Si interfaces.

Conductivity Enhancement in Thin Silicon-on-Insulator Layer Embedding Artificial Dislocation Network

AbstractA nanometer-scale dislocation network is artificially formed in thin top Si layer of silicon-on-insulator (SOI) structure, and effect of the dislocation network on the transport property is examined from the viewpoint of nanodevice applications. The artificial network of screw dislocations was formed in the Si layer using a wafer bonding of a pair of (001) SOI wafers with a slight misalignment of the in-plane crystalline directions to cause a lattice mismatch. The transmission electron microscopy clearly revealed the formation of dislocation network at the bonding interface with the period less than ∼20 nm. The dislocation network was found to enhance the conductivity in the Si bicrystal layer more than one order of magnitude in comparison with that in the monocrystal layer free from the dislocations. The enhanced conductivity is probably derived from an increased concentration of electrons around the dislocations due to the formation of donor-like gap states.

N+/P and P+/N Junctions in Strained Si on Strain Relaxed SiGe Buffers: the Effect of Defect Density and Layer Structure

AbstractThe electrical performance of junctions in SiGe Strain Relaxed Buffers (SRB's) with a strained Si top layer is investigated. Most of the SRB's grown in this experiment use a thin C-doped SiGe layer, which allows to fabricate thin (∼250nm) SRB's with a high relaxation degree. The effects of Threading Dislocation Density (TDD) and C-rich layer depth on the electrical behaviour of n+/p and p+/n junctions are studied. The C atoms in the junction's Space Charge Region (SCR) give rise to defects and induce a noticeable increase in the leakage. The effect of the TDD on the leakage in n+/p junctions is linear over the complete voltage range applied, while for p+/n junctions, only a small effect on leakage is measured at V=1V reverse for TDD's below 1×107cm-2. For low reverse voltages, the current varies more linearly with TDD.

Formation of silicon on plasma synthesized aluminum nitride structure by ion cutting

The application of silicon-on-insulator (SOI) substrates to high-power integrated circuits is hampered by self-heating effects due to the poor thermal conductivity of the buried SiO2 layer. We propose to replace the buried SiO2 layer in SOI with a plasma synthesized AlN thin film to mitigate the self-heating penalty. The AlN films synthesized on silicon by metal plasma immersion ion implantation and deposition exhibit outstanding surface topography and excellent insulating characteristics. Using a modified direct bonding process in conjunction with hydrogen-induced layer transfer, a silicon-on-AlN structure has been successfully fabricated. Cross-sectional high-resolution transmission electron microscopy, x-ray photoelectron spectroscopy, and spreading resistance profiling results reveal a uniform buried AlN layer beneath a single crystal Si overlayer. The interfaces between the top Si layer, buried AlN layer, and Si substrate are smooth and sharp. Moreover, the use of relatively thick buried AlN layer bodes well for SOI wafers in high voltage and high power applications.

Formation of silicon-on-aluminum nitride using ion-cut and theoretical investigation of self-heating effects

We propose to replace the buried SiO 2 layer in silicon-on-insulator (SOI) with a plasma-synthesized AlN thin film to mitigate the self-heating penalty. The AlN films synthesized on Si by metal plasma immersion ion implantation–deposition (Me-PIIID) exhibit outstanding surface topography and excellent insulating characteristics. Using direct bonding process and the hydrogen-induced layer transfer method, a silicon-on-AlN (SOAN) structure has been successfully fabricated. Cross-sectional high-resolution transmission electron microscopy (HRTEM), X-ray photoelectron spectroscopy (XPS) depth profiles and spreading resistance probe (SRP) reveal that a uniform buried AlN layer is under a single crystal Si overlayer. The interfaces between the top Si layer, buried AlN layer, and Si substrate are smooth and sharp. In addition, the new SOAN device has been verified in two-dimensional device simulation and demonstrates that the self-heating penalty of SOI can indeed be reduced using SOAN substrates.

Hydrogen annealing effects on epitaxy of SOI wafer

Thick silicon on insulator (SOI) wafers have been fabricated by chemical vapor deposition (CVD) after separation by implantation of oxygen (SIMOX) process. The hydrogen annealing effects on epitaxial Si layer were studied. The hydrogen annealing could remove the surface damages of substrate caused by SIMOX process and provide a smoother epitaxial substrate. The number of dislocations and stacking faults in the epitaxial layer decreased remarkably by hydrogen annealing SOI substrate. Meanwhile, compared with other reports, our hydrogen annealing did not degrade the buried oxide layer and top Si layer of SOI substrate.