Si-on-insulator Research Articles

{110}-facets formation by hydrogen thermal etching on sidewalls of Si and strained-Si fin structures

Si-fin structures for multigate metal-oxide-semiconductor field effect transistors (MOSFETs) with smooth and vertical sidewalls composed of {110} facets were obtained by an anisotropic gas etching in atmospheric hydrogen ambient at 925–1000°C on strained and unstrained (001) Si-on-insulator (SOI) substrates. {110} facets emerged due to higher etching rate for higher-order crystalline plane adjacent to {110} planes. The facet formation effectively eliminated the fin-width variation originating from the lithography process. The uniaxial stress along the fins on the strained SOI substrate was found to be preserved during the process, indicating the availability of this technique for fabrication of multigate MOSFETs with strained-fin channels.

Proof of the existence of large complete band gaps in high frequency silicon phononic crystal plates

We show, for the first time, the evidence of the existence of large phononic band gaps (PBGs) in two‐dimensional phononic crystal (PC) plates formed by etching a hexagonal (honeycomb) array of air holes through a free standing plate of silicon (Si). A CMOS compatible fabrication process is used on a Si on insulator (SOI) substrate to realize the PC devices. More than 30 dB attenuation is observed for eight periods of the hexagonal lattice PC at high frequency region, i.e. 133 MHz with a band gap to mid gap ratio of 25%. We show that the experimental results agree very well with the theoretical predictions for the PBG. This result opens a new direction in the implementation of high frequency practical PC structures for a variety of applications especially wireless communication, and sensing.

Fabrication of Thick Germanium-on-Insulator (GeOI) Substrates

Fabrication of germanium-on-insulator (GeOI) substrates with a 160-nm-thick Ge layer is reported. Such thick GeOI substrates were fabricated by thermal intermixing and subsequent condensation of epitaxially grown high-Ge- content SiGe on Si-on-insulator (SOI) substrates. Transmission electron microscopy revealed that the GeOI layer was single crystalline. The high-resolution rocking curve and reciprocal lattice map obtained from X-ray diffraction measurements showed a relaxed GeOI. This was further confirmed by micro-Raman measurements, where the Ge-Ge optical phonon peak shift represented a nearly strain-free Ge layer. Using this methodology, GeOI substrates with Ge layers 120–160 nm thick have been fabricated with thickness variations of less than 4 nm across 200 mm wafers.

Characterization of Strain for High-Performance Metal–Oxide–Semiconductor Field-Effect-Transistor

Strain evaluation in a small area is required because the extremely short channel length in state-of-the-art metal–oxide–semiconductor field-effect transistors (MOSFETs) leads to a narrow and shallow channel region. The strain in this limited area strongly affects the device performance owing to carrier mobility modification. We used UV–Raman spectroscopy with a quasi-line-shape excitation source and a two-dimensional charge-coupled-device detector in order to evaluate the strain distribution in Si or Si-on-insulator (SOI) substrates with a patterned SiNx film. As results, the strain was concentrated at the SiNx/Si interface and SiNx film pattern edge. A large tensile (compressive) strain was induced by the SiNx film with inner tensile (compressive) stress in the space region that corresponds to a channel region of the n- or p-MOSFETs. We assume that these large strains in the space region are the origin of the mobility enhancement in n- or p-MOSFETs. Furthermore, in addition to the size effect of channel length, we confirmed that the strain could be controlled by changing SiNx film thickness, film stress, and the substrate (SOI or bulk-Si). The quantitative evaluation of strain by means of simulation is also discussed.

Evaluation of Strain in Si-on-Insulator Substrate Induced by Si3N4 Capping Film

Strain introduced to Si-on-insulator (SOI) substrates by Si3N4 capping film was evaluated by UV-Raman spectroscopy. The induced strain became larger with increasing Si3N4 film thickness. SOI substrates originally had tensile strain and the Si3N4 cap shifted the strain toward the compressive direction. The induced strain was larger in thinner SOI substrates with the same thickness of the Si3N4 capping film. In the SOI substrates with patterned Si3N4 film, the strain was in different directions between the regions with and without Si3N4 film; i.e., if the strain was compressive in the region beneath the Si3N4 film, it was tensile beneath the space between the Si3N4 lines. We also evaluated substrates after Si3N4 patterning with a high spatial resolution of 200 nm, and observed strain enhancement near the pattern edge on both sides.

Investigation of SOI Substrates Incorporated with Buried MoSi2 for High Frequency SiGe HBTs

Highly arsenic-doped Si-on-insulator (SOI) substrate incorporated with buried MoSi2 layers is fabricated aiming at decreasing the collector series resistance of SiGe heterojunction bipolar transistors (HBTs) on SOI, thereby enhancing cutoff frequency (fT) performance and increasing the maximum value of fT (fTMAX). The fT performance at medium current is enhanced and current required for fT = 15 GHz is reduced by half. The value of fTMAX is improved by 30%.

Solid phase epitaxy during Ge condensation from amorphous SiGe layer on silicon-on-insulator substrate

We report the solid phase epitaxial growth of silicon germanium (SiGe) layer during condensation/oxidation of sputter deposited amorphous SiGe layer on Si on insulator (SOI). The amorphous SiGe layer was first converted into polycrystalline film by preannealing and high temperature oxidation process. The solid phase epitaxial growth occurs during further oxidation/annealing process of polycrystalline SiGe on the Si on insulator substrate. A final thickness of about 1040Å of single crystalline SiGe is achieved with initial amorphous SiGe and SOI of thickness of 1000 and 740Å, respectively SiGe with 60% Ge concentration was achieved on further condensation followed by cyclic annealing to eliminate the defects formed in the layer.

Misfit dislocation dipoles in Si/SiGe/Si heterostructures on SOI

Transmission electron microscopy (TEM) and synchrotron radiation double-crystal topography (SRDT) have been employed to investigate Si/SiGe/Si heterostructures grown by ultra-high vacuum chemical vapor deposition (UHVCVD) on bonded Si-on-insulator (SOI) wafers. A configuration of misfit dislocation dipoles is observed by high-resolution transmission electron microscopy (HRTEM). The dislocation dipoles are mostly of 60° type and three types of 60° dislocation dipoles, extrinsic, intrinsic, and null, are presented. Dark-field images (DFIs) indicate no lateral compositional modulations but strain distribution appearing in the SiGe layer, which is supported by the SRDT topograph. We suggest that the lateral strain modulation in the SiGe layer and subsequent annealing play an important role in the introduction of the dislocation dipoles.

Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime ( τ g) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron–hole droplet in the band-edge emission.

Demonstration of Hybrid Silicon-on-Silicon Carbide Wafers and Electrical Test Structures with Improved Thermal Performance

AbstractMultiple 50 mm hybrid Si-on-SiC substrates consisting of thin film [100] Si (1 μm) on bulk semi-insulating [0001] 6H-SiC wafers were fabricated using low-temperature (150°C) wafer bonding and slicing techniques. A set of samples were prepared comparing various thicknesses of SiO2 (60, 120, 190, 240 and 520 nm) as an intermediate bonding layer between the two materials. A variety of test structures such as Van der Pauw structures, linear transfer-length measurement arrays and resistors were fabricated in the Si layers using standard Si processing (such as lithography, B-diffusion, etching and oxidation) in order to characterize the robustness as well as the electrical and thermal properties of the hybrid substrates. Bulk Si and Si-on-insulator (SOI) substrates were used for comparison. We report the Si layers on the hybrid Si-on-SiC substrates to be device-grade in terms of mobility and crystal structure, and that their device-to-device electrical isolation properties are superior to those of bulk Si and comparable to those of SOI. Furthermore, electrical test structures on hybrid Si-on-SiC substrates exhibit vastly superior heat dissipation compared to equivalent devices on bulk Si or SOI. Specifically, the temperature rise can be as much as 102°C lower in resistor devices made on Si-on-SiC (Tj= 191°C) compared to on bulk Si (Tj= 293C) under high-power density operation (67 kW/cm2). We also describe the effects of intermediate oxide thickness on thermal resistance.

Effect of implantation energy and dose on low-dose SIMOX structures

In order to form silicon (Si)-on-insulator (SOI) layers with various thicknesses, oxygen implantation with doses between 1.0×1017/cm2 and 6.0×1017/cm2 and at energies between 40 and 240 keV has been carried out into 300 mm diameter (100)Si wafers at a temperature of 560 °C. After implantation, Si wafers are annealed in dry Ar mixed with 1% O2 at a temperature of 1350 °C for 4 h. The quality of buried oxide (BOX) layers and the microstructure in implanted layers before and after annealing is characterized by transmission electron microscopy. The results reveal that the appreciable number of threading dislocations (TDs) is generated in SOI layers implanted at energies above 200 keV under the optimum dose-energy conditions for the continuous BOX layer formation. Whereas, in the case of discontinuous BOX layers, the TD generation is observed in samples implanted at energies above 120 keV. The generation of TDs is discussed with the emphasis on the effect of implantation energy.

Evaluation of commercial ultra-thin Si-on-insulator wafers using laser confocal inspection system

Commercially available ultra-thin (50 nm) Si-on-insulator (SOI) wafers were evaluated using a laser confocal inspection system. The defect distribution and defects were observed for both bonded SOI and separation-by-implanted-oxygen (SIMOX) wafers. Some of defects were marked using the system's marking function and evaluated using transmission electron microscopy after the samples were prepared using focused ion beam thinning. The most serious defects observed in both types of wafers were voids. Small defects such as dislocations were also detected. The inspection system is non-destructive and therefore promising for use in pre- and in-line monitoring systems.

Growth of SiGe-on-insulator and its application as a substrate for epitaxy of strained-Si layer

We report on a simple approach for fabrication of SiGe-on-insulator (SGOI), which contains the growth of Ge on a Si-on-insulator (SOI) substrate and following high-temperature annealing. We discuss the guiding principle for choice of the processing parameters to obtain high-quality SGOI. Furthermore, SGOI was utilized as a substrate for subsequent epitaxial growth of a strained-Si layer. As a result, fluctuation of the strain in the Si film on SGOI was found to be suppressed compared with that on a conventional SiGe virtual substrate, which shows that SGOI grown by our method is promising for the substrate to grow high-mobility strained-Si channel layers.

Method for Detecting Defects in Silicon-On-Insulator Using Capacitance Transient Spectroscopy

A method for detecting defects such as interface states and a deep trap in Si-on-insulator (SOI) has been proposed, which is based on deep-level transient spectroscopy (DLTS) analysis of the metal-oxide semiconductor (MOS) structure. It is shown, for a bonded p-type SOI wafer consisting of 5 µm top-Si (T-Si) and 1 µm buried oxide (BOX) layers, that the interface state densities between T-Si/BOX and BOX/back-Si (B-Si) can be measured. Furthermore, the validity of this DLTS technique for the detection of a discrete deep level has been confirmed by using a Fe-doped SOI wafer. It is shown that the Fe concentration in B-Si is consistent with that of bulk Si, while the Fe concentration in T-Si shows significant enhancement. Through these investigations of SOI wafers, the validity of this DLTS method has been demonstrated.

Fabrication and characterization of micro-heaters with low-power consumption using SOI membrane and trench structures

Abstract This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal microelectromechanical system (MEMS) applications using Si-on-insulator (SOI) membrane and trench structures. The micro-heaters are based on a thermal measurement principle and contain thermal isolation regions of 10 μm thick Si membranes consisting of oxide-filled trenches in the SOI membrane rim. The micro-heaters were fabricated with Pt-RTD on the same substrate via the MgO buffer layer between the Pt thin-film and SiO2 layer. The thermal characteristics of micro-heaters with trench-free SOI membrane structure was 280 °C at an input power 0.9 W; and in the presence of 10 trenches, it was 580 °C due to the reduction of the external thermal loss. Therefore, a micro-heater with trenches in the SOI membrane rim structure provides a powerful and versatile alternative technology for enhancing the performance of micro-thermal sensors and actuators.

Dislocation-free relaxed SiGe-on-insulator mesa structures fabricated by high-temperature oxidation

Relaxed SiGe-on-Insulator (SGOI) mesa structures were fabricated using mesa etching and successive high-temperature oxidation of SiGe layer on a Si-on-insulator (SOI) substrate for strained SOI (SSOI) metal–oxide–semiconductor field effect transistors (MOSFETs). In this procedure, the oxidation induces an increase in Ge fraction in the SiGe layer due to the rejection of Ge atoms from the oxide layer, while the mesa isolation enhances the lattice relaxation in the SiGe mesa. As a consequence, almost fully relaxed SGOI mesa structures with the Ge fraction up to 0.35 were obtained without introducing dislocations and surface undulation. Raman measurements revealed that a higher relaxation has been obtained for smaller and thicker mesas as well as at higher oxidation temperature. The experimental results were qualitatively explained by a relaxation model in which a strained SiGe island expands laterally without introducing dislocations on a plastic substrate. Based on this model, the applicability of this method to the fabrication of scaled MOSFETs was examined. In conclusion, this technique is promising for the fabrication of dislocation-free SGOI layers for scaled SSOI-MOSFETs without using any processes which are incompatible with conventional MOSFET processes.

Long-Wavelength SiGe/Si MQW Resonant-Cavity-Enhanced Photodiodes (RCE-PD)

Si1-xGex/Si optoelectronic devices are promising for the monolithic integration with silicon-based microelectronics. SiGe/Si MQW RCE-PD (Resonant-Cavity-Enhanced photodiodes) with different structures were investigated in this work. Design and fabrication of top- and bottom-incident RCE-PD, such as growth of SiGe MQW (Multiple Quantum Wells) on Si and SOI (Si on insulator) wafers, bonding between SiGe epitaxial wafer and SOR (Surface Optical Reflector) consisting Of SiO2/Si DBR (Distributed Bragg Reflector) films on Si, and performances of RCE-PD, were presented. The responsivity of 44mA/W at 1.314 mum and the FWHM of 6nm were obtained at bias of 10V. The highest external quantum efficiency measured in the investigation is 4.2%.

Fabrication of CoSi2-Buried-Metal-Layer Si Substrates for Infrared Reflection Absorption Spectroscopy by Wafer-Bonding

Infrared reflection absorption spectroscopy (IRRAS) using buried metal layer substrates (BML) is one of the high resolution and high sensitive surface vibration spectroscopy techniques. A unique characteristic is the wide frequency range including the so-called finger print region. The CoSi2 Si(100) BML substrates fabricated by Co ion implantation have been used to date. However, the technique has several problems such as the resultant surface roughness due to the ion implantation damage. To solve these problems, in this work, we have examined the fabrication of BML substrates with atomic-level flat surfaces by the wafer-bonding between a Co deposited Si(100) wafer and a Si on insulator (SOI) wafer. Self-assembled alkyl monolayers (SAMs) of octadecyltrichlorosilane and octenyltrichlorosilane were deposited on the fabricated BML substrate surface. Good BML-IRRAS spectra were observed in the wide frequency range from stretching to bending regions. It was also found that well-ordered SAMs were deposited.

Ultrathin body sige-on-insulator pmosfets with high-mobility sige surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.

Reduction of cracks in GaN films grown on Si-on-insulator by lateral confined epitaxy

GaN was grown by metal organic chemical vapor deposition (MOCVD) on plain Si-on-insulator (SOI) substrates, and on SOI which was pre-patterned for lateral confined epitaxy (LCE), with square mesas, separated by dip trenches. It was found that GaN films grown on plain SOI exhibit reduced crack density. Moreover, using LCE on SOI substrates dramatically increases the crack-free area of the layer. Areas of 100 μm×100 μm were grown completely crack free, and stress was released by strong bending of the GaN/Si/SiO 2 composite islands.