Si Control Devices Research Articles

A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization

A study is made of noise in p- and n-channel transistors incorporating SiGe surface and buried channels, over the frequency range f=1 Hz–100 kHz. The gate oxide is grown by low temperature plasma oxidation. Surface n-channel devices are found to exhibit two noise components namely 1/ f and generation–recombination (GR) noise. It is shown that the 1/ f noise component is due to fluctuations of charge in slow oxide traps whilst bulk centers located in a thin layer of the semiconductor close to the channel, give rise to the GR noise component. The analysis of the noise data gives values for the density D ot of the oxide traps in the SiGe and Si nMOSFETs of the order 1.8×10 12 and 2.5×10 10 cm −2 (eV) −1, respectively. The density D GR of the bulk GR centres is equal to 3×10 10 cm −2 in both the SiGe and Si devices. The electron and hole capture cross-sections for these centres as well as their energy level and their depth below the oxide/semiconductor interface are also the same in the devices of both types. This suggests that those GR centers are of the same nature in all devices studied. p-Channel devices show different behaviour with only a 1/ f noise component apparent in the data over the same frequency range. Buried SiGe channel and Si control devices exhibit quite low and similar slow state densities of the order low to mid 10 10 cm −2 (eV) −1 whereas surface p-channel devices show even higher slow state densities than n-channel counterparts. The Hooge noise characterized by the Hooge coefficient α H=2×10 −5 is also detected in some buried p-channel SiGe devices.

Improving SiO2/SiGe interface of SiGe p-metal–oxide–silicon field-effect transistors using water vapor annealing

SiGe p-metal–oxide–silicon field-effect transistors (p-MOSFETs) were fabricated with ultrathin thin (∼20 Å) remote plasma chemical vapor deposition gate oxides deposited directly on SiGe. A low temperature water vapor annealing was used to improve the SiO2/SiGe interface and performance of SiGe p-MOSFETs. After the wet annealing, dangling Si and Ge bonds at the interface are passivated by atomic hydrogen, the threshold voltage of SiGe p-MOSFETs decreases from −0.39 to −0.20 V, the subthreshold slope from 117 to 87 mV/dec, and more than 20% output current enhancement is observed in these SiGe p-MOSFETs compared with Si control devices.

Transient thermal simulations of a three-dimensional unit cell in power control systems and high-power microwave devices

Detailed numerical assessment is given supporting the need to go beyond two-dimensions for numerically analyzing the electrothermal characteristics of power control devices employed in high-performance paralleling layout topology, and high-power microwave devices in monolithic microwave integrated circuits (MMIC). An accurate understanding of transient thermal characteristics, particularly the transient power-overload failure mechanism, is needed and requires the use of three-dimensional (3-D) transient electrothermal simulations. This will enable the design optimization of these power control devices for hardening against failure due to external fault conditions. We have compared the characteristic thermal speed response of Si, SiC, and GaN power control devices under short-circuit conditions, using 3-D time-dependent simulations. Such improved thermal simulation is also very important for high-power microwave devices and MMIC. Calibration of our numerical techniques with experiment is implemented using atomic force microscopy temperature measurements. The consistent agreement between measured values and simulated results indicates the need to couple detailed numerical simulation with high-resolution measurement technique, especially in identifying heat-flow bottlenecks. This will allow taking into account the actual thermal coupling of semiconductor substrate with the base plate and surrounding environment, where the fixed-temperature boundary condition usually applied at the substrate is not valid.

Bandgap engineering in vertical P-MOSFETs

Bandgap engineering in vertical P-MOSFETs has been investigated in view of suppressing the short channel effects, floating body effect, and improving the drive current. SiGe source heterojunction P-MOSFETs have been used to suppress the short channel effects for sub-100 nm devices. While the leakage is reduced, the drive current is also reduced due to the use of a heterojunction. In this paper, we discuss a SiGe source heterojunction vertical P-MOSFET with a few nanometers thick Si cap. With this device structure, the absence of the heterojunction-induced potential barrier right below the oxide interface improves the drive current substantially while the drain induced barrier lowering effect and floating body effect are still suppressed. To further improve the drive current of the device, a SiGe/Si cap was added to the SiGe heterojunction P-MOSFET. We call this device a high mobility heterojunction MOSFET (HMHJT). Compared with the Si control device, the HMHJT has higher drive current and less off-state current at the same time.

Vertical p-type high-mobility heterojunction metal–oxide–semiconductor field-effect transistors

We have fabricated a vertical p-channel metal–oxide–semiconductor field-effect transistor called high-mobility heterojunction transistor (HMHJT). Compared with a Si control device, reduced short channel effects, reduced floating body effect, and high drive current have been achieved with this device structure. A SiGe/Si heterojunction barrier at the source/bulk junction suppresses drain induced barrier lowering and bulk punchthrough, which are significant problems for sub-100 nm devices. A SiGe source also helps to reduce the charge built-up in the floating body. The higher mobility in a strained SiGe channel and the absence of a hetero-barrier between the source and channel result in higher drive current. The fabricated HMHJT has a 60% higher drive current at VDS=VGS−VT=−1.6 V, and a 70× lower off-state leakage current at VDS=−1.6 V and VGS=0.0 V, compared with the Si control device.

Electron mobility enhancement in strained SiGe vertical n-type metal–oxide–semiconductor field-effect transistors

We have fabricated strained SiGe vertical n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 μm without sophisticated lithography and the whole process is compatible with a regular complementary metal–oxide–semiconductor process. The drive current for these devices has been observed to be enhanced by 50% compared with Si control devices on the same wafer. Electron mobility enhancement in the out-of-plane direction for the strained SiGe layer was demonstrated in this study.

Hole and electron mobility enhancement in strained SiGe vertical MOSFETs

We have fabricated strained SiGe vertical P-channel and N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 /spl mu/m without sophisticated lithography and the whole process is compatible with a regular CMOS process. The enhancement for the hole and electron mobilities in the direction normal to the growth plane of strained SiGe over that of bulk Si has been demonstrated in this vertical MOSFET device structure for the first time. The drain current for the vertical SiGe MOSFETs has been found to be enhanced by as much as 100% over the Si control devices and the drain current for the vertical SiGe NMOSFETs has been enhanced by 50% compared with the Si control de, ices on the same wafer. The electron mobility enhancement in the normal direction is not as significant as that for holes, which is in agreement with theoretical predictions.

SiGe heterojunction vertical p-type metal–oxide–semiconductor field-effect transistors with Si cap

SiGe source heterojunction p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) have been used before to suppress the short channel effect for sub-100 nm devices. While the leakage is reduced, the drive current is also reduced due to the heterojunction. In this letter, we discuss a SiGe source heterojunction vertical p-MOSFET with a few nanometers thick Si cap. With this device structure, the absence of the heterojunction-induced potential barrier right below the oxide interface improves the drive current substantially while the drain induced barrier lowering (DIBL) effect and floating body effect are still suppressed. The electrical characterization of the device shows it exhibits higher drive current and less DIBL compared with a Si control device.

High temperature formed SiGe p-MOSFETs with good device characteristics

We have used a simple process to fabricate Si/sub 0.3/Ge/sub 0.7//Si p-MOSFETs. The Si/sub 0.3/Ge/sub 0.7/ is formed using deposited Ge followed by 950/spl deg/C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm/sup 2//Vs is obtained from the Si/sub 0.3/Ge/sub 0.7/ p-MOSFET that is /spl sim/two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 /spl Aring/ Si/sub 0.3/Ge/sub 0.7/ thermal oxide grown at 1000/spl deg/C has a high breakdown field of 15 MV/cm, low interface trap density (D/sub it/) of 1.5/spl times/10/sup 11/ eV/sup -1/ cm/sup -2/, and low oxide charge of 7.2/spl times/10/sup 10/ cm/sup -2/. The source-drain junction leakage after implantation and 950/spl deg/C RTA is also comparable with the Si counterpart.

Hole confinement and low-frequency noise in SiGe pFETs on silicon-on-sapphire

We present the dc, ac, and low-frequency noise characteristics of SiGe channel pFETs on silicon-on-sapphire (SOS). The SiGe pFETs show higher mobility, transconductance, and cutoff frequency compared to the Si control devices. A significant reduction in low-frequency (1/f) noise is observed in the SiGe pFETs, and understood to be the result of a lower border trap density sampled at the Fermi-level due to the valence band offset. The linear g/sub m/ of the SiGe pFET's at 85 K shows a secondary peak which is attributed to the turn-on of the surface channel.

Characteristics of Surface-Channel Strained Si1-yCyn-MOSFETS

AbstractThe first demonstration of n-MOSFETs fabricated using strained Si1-yCy surface channels is reported. Tensile-strained Si1-yCy layers with substitutional carbon contents up to 0.8 atomic percent were epitaxially grown on <100> Si substrates by rapid thermal chemical vapor deposition, using silane and methylsilane as the silicon and carbon precursors. n-MOSFETS were fabricated using standard MOS processing with reduced thermal exposure to minimize the possibility of strain relaxation. A remote plasma CVD oxide was employed to form the gate oxide. The Si1-yCy devices exhibit electrical characteristics that are typical for Si n-MOSFETs, with good turn-on and subthreshold characteristics. MOS capacitance-voltage analysis demonstrates comparable oxide interface qualities for the Si1-yCy and Si control devices. No carbon-related leakage current is observed in source and drain diode junctions. Characterization of the MOSFET electron inversion layer mobility at room temperature shows comparable mobilities, within the sensitivity of the measurement, for the Si1-yCy and Si control devices. This is in contrast to the mobility enhancement observed in n-MOSFETs fabricated using tensile- strained Si grown on relaxed Si1-xGex layers. At low temperatures, the inversion layer mobility of Si1-yCy devices is lower than that of the Si controls, and appears to be affected by Coulomb and possibly random alloy scattering.

A deep submicron Si/sub 1-x/Ge/sub x//Si vertical PMOSFET fabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si/sub 1-x/Ge/sub x/ channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si/sub 1-x/Ge/sub x//Si transistors can be fabricated with channel lengths below 0.2 /spl mu/m without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si/sub 1-x/Ge/sub x/ over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's.

Electrical properties of GeSi surface- and buried-channel p-MOSFETs fabricated by Ge implantation

The electrical properties of surface- and buried-channel p-MOSFETs containing strained GeSi heterostructures synthesized by high-dose Ge implantation and solid phase epitaxial growth have been investigated. Compared with Si control devices on the same chips, GeSi transistors exhibited improved performance: the channel hole mobility and linear transconductance was up to 18% higher for surface-channel GeSi transistors, and up to 12% higher for buried-channel GeSi p-MOSFETs, than for equivalent Si devices. Ion-beam synthesis of GeSi strained layers therefore offers an attractive means for realising improved device performance in conventional Si device structures.

High mobility Si1-xGex PMOS transistors to 5K

P-channel Si 1-x Ge x MOSFETs with peak Ge content x=0.3, 0.4, and 0.5 have been fabricated via MBE and experimentally characterized from room temperature down to 5K. Mobility enhancements relative to identically processed Si controls were largest at the lowest temperatures. The highest mobility measured, μ FE =1622 cm 2 /V.sec for the x=0.3 SiGe device, was approximately a factor of four higher than the mobility of the Si control devices. Peak mobility decreased as the fraction of Ge in the SiGe channel layer increased for the range of concentrations studied here

Temperature and scaling behavior of strained-Si N-MOSFET's

Summary form only given. The device characteristics of N-MOSFETs fabricated in strained-Si have been investigated as a function of temperature and gate length. It is found that the low field mobility is enhanced compared to Si control devices at temperatures down at 20 K. For moderate fields, g/sub m/ is enhanced at all measured temperatures, for effective gate lengths down to 0.8 mu m (L/sub drawn/=1.5 mu m). At high power density, however, the devices exhibit a negative differential output resistance. The thermal conductivity of the relaxed Si/sub 1-x/Ge/sub x/ buffer layers is estimated by fitting polysilicon resistor characteristics to a first order model. >

Graded-bandgap SiGe bipolar transistor fabricated with germanium ion implantation

A graded-bandgap SiGe heterojunction bipolar transistor (HBT) is fabricated using Ge+ implantation. The maximum current gain and the maximum cutoff frequency are 40 and 8 GHz respectively, while those of the Si control device are 100 and 11 GHz. This relatively high cutoff frequency is obtained for the SiGe HBT despite considerable defects in the emitter and base regions, and is attributed to the drift field in the base region resulting from the graded bandgap.