Si Complementary Metal Oxide Semiconductor Research Articles

Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing.

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its2D counterpart.

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays.

High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide-semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs). The fabricated scandium (Sc)-contacted A-CNT N-FET with a 100 nm gate length exhibits an on-state current (Ion) of 800 μA/μm and a peak transconductance (gm) of 250 μS/μm, representing the highest performance of CNT-based N-FETs to date. Moreover, CMOS technology has been developed to realize N- and P-FETs with symmetric high performance based on A-CNTs. The fabricated A-CNT CMOS FETs show electron and hole mobilities of 325 and 241 cm2 V-1 s-1, respectively, which are slightly higher than the corresponding values of Si CMOS transistors. Our scalable fabrication of A-CNT CMOS FETs with comparable electronic performance to Si CMOS will promote the application of CNT-based electronics in digital ICs.

3D Bragg Coherent Diffraction Imaging of Extended Nanowires: Defect Formation in Highly Strained InGaAs Quantum Wells.

InGaAs quantum wells embedded in GaAs nanowires can serve as compact near-infrared emitters for direct integration onto Si complementary metal oxide semiconductor technology. While the core-shell geometry in principle allows for a greater tuning of composition and emission, especially farther into the infrared, the practical limits of elastic strain accommodation in quantum wells on multifaceted nanowires have not been established. One barrier to progress is the difficulty of directly comparing the emission characteristics and the precise microstructure of a single nanowire. Here we report an approach to correlating quantum well morphology, strain, defects, and emission to understand the limits of elastic strain accommodation in nanowire quantum wells specific to their geometry. We realize full 3D Bragg coherent diffraction imaging (BCDI) of intact quantum wells on vertically oriented epitaxial nanowires, which enables direct correlation with single-nanowire photoluminescence. By growing In0.2Ga0.8As quantum wells of distinct thicknesses on different facets of the same nanowire, we identified the critical thickness at which defects are nucleated. A correlation with a traditional transmission electron microscopy analysis confirms that BCDI can image the extended structure of defects. Finite element simulations of electron and hole states explain the emission characteristics arising from strained and partially relaxed regions. This approach, imaging the 3D strain and microstructure of intact nanowire core-shell structures with application-relevant dimensions, can aid the development of predictive models that enable the design of new compact infrared emitters.

Si-CMOS-compatible 2D PtSe2-based self-driven photodetector with ultrahigh responsivity and specific detectivity

Photodetectors (PDs) based on two-dimensional (2D) materials are attracting considerable research interest due to the unique properties of 2D materials and their tunable spectral response. However, their performance is not outstanding enough, and the compatibility of their fabrication process with Si-complementary metal oxide semiconductor (CMOS) process flow needs evaluation. Here, we report an unprecedented high-performance, air-stable, self-driven, and broadband room-temperature PD based on the architecture of the PtSe2/ultrathin SiO2/Si heterojunction. The PD exhibits a very prominent responsivity of 8.06 A W−1, a truly high specific detectivity of 4.78 × 1013 cm Hz1/2 W−1, an extremely low dark current of 0.12 pA, and a fantastic photocurrent/dark current ratio of 1.29 × 109 at zero bias. The measured photocurrent responsivities at wavelengths of 375, 532, 1342, and 1550 nm are 2.12, 5.56, 18.12, and 0.65 mA W−1, respectively. Moreover, the fabricated 9 × 9 device array not only illustrates the very high uniformity and reproducibility of the PDs but also shows great potential in the field of ultraviolet-visiblenear infrared illumination imaging applications with a fabrication fully compatible with Si-CMOS technologies. Our design of the PtSe2/ultrathin SiO2/Si heterojunction PD greatly suppresses dark current, improves the diode ideality factor, and increases the potential barrier. Accordingly, it paves the way for a general strategy to enhance the performance of PDs used in novel optoelectronic applications.

Sn content gradient GeSn with strain controlled for high performance GeSn mid-infrared photodetectors

GeSn detectors have attracted a lot of attention for mid-infrared Si photonics, due to their compatibility with Si complementary metal oxide semiconductor technology. The GeSn bandgap can be affected by Sn composition and strain, which determines the working wavelength range of detectors. Applying the Sn content gradient GeSn layer structure, the strain of GeSn can be controlled from fully strained to completely relaxed. In this work, the strain evolution of GeSn alloys was investigated, and the effectiveness of gradually increasing Sn composition for the growth of high-Sn-content GeSn alloys was revealed. Relaxed GeSn thick films with Sn composition up to 16.3% were grown, and GeSn photodetectors were fabricated. At 77 K, the photodetectors showed a cutoff wavelength up to 4.2 μm and a peak responsivity of 0.35 A/W under 1 V at 2.53 μm. These results indicate that GeSn alloys grown on a Sn content gradient GeSn structure have promising application in mid-infrared detection.

Advancement in Silicon Integrated Photonics Technologies for Sensing Applications in Near-Infrared and Mid-Infrared Region: A Review

Exploration and implementation of silicon (Si) photonics has surged in recent years since both photonic component performance and photonic integration complexity have considerably improved. It supports a wide range of datacom and telecom applications, as well as sensors, including light detection and ranging, gyroscopes, biosensors, and spectrometers. The advantages of low-loss Si WGs with compact size and excellent uniformity, resulting from the high quality and maturity of the Si complementary metal oxide semiconductor (CMOS) environment, are major drivers for using Si in photonics. Moreover, it has a high refractive index and a reasonably large mid-infrared (MIR) transparency window, up to roughly 7 μm wavelength, making it beneficial as a passive mid-IR optical material. Several gases and compounds with high absorption properties in the MIR spectral region are of prodigious curiosity for industrial, medicinal, and environmental applications. In comparison to current bulky systems, the implementation of Si photonics devices in this wavelength range might allow inexpensive and small optical sensing devices with greater sensitivity (S), power usage, and mobility. In this review, recent advances in Si integrated photonic sensors working in both near-infrared (NIR) and MIR wavelength ranges are discussed. We believe that this paper will be valuable for the scientific community working on Si photonic sensing devices.

Heterogeneous and Monolithic 3D Integration of III-V-Based Radio Frequency Devices on Si CMOS Circuits.

Next-generation wireless communication such as sixth-generation (6G) and beyond is expected to require high-frequency, multifunctionality, and power-efficiency systems. A III-V compound semiconductor is a promising technology for high-frequency applications, and a Si complementary metal-oxide-semiconductor (CMOS) is the never-beaten technology for highly integrated digital circuits. To harness the advantages of these two technologies, monolithic integration of III-V and Si electronics is beneficial, so that there have been everlasting efforts to accomplish the monolithic integration. Considering that the on horizon 6G wireless communication requires faster and more energy-efficient system-on-chip technologies, it is imperative to realize a radio frequency (RF) system in which III-V technology and Si CMOS technology are integrated at a device level. Here we report heterogeneous and monolithic three-dimensional (3D) analog/RF-digital mixed-signal integrated circuits that contain two types of InGaAs high-electron-mobility transistors (HEMTs) designed for high fT and fMAX in the top and Si CMOS mixed-signal circuits consisting of an analog-to-digital converter and digital-to-analog converter in the bottom. A high unity current gain cutoff frequency of 448 GHz and unity power gain cutoff frequency of 742 GHz have been achieved by the fT oriented and fMAX oriented InGaAs HEMTs, respectively, without being affected by mixed-signal interference. At the same time, the bottom Si CMOS circuits provide valid signals without any performance degradation by the integration process.

Review of Ka-Band Power Amplifier

With the increase in the demand for high-speed transmission communication, satellite communication is developing rapidly. Because of the bandwidth capacity, the K/Ka band is considered the mainstream frequency band of satellite communication. The performance of a power amplifier (PA) directly affects the power of the transmitter, so the application of a power amplifier in Ka-band satellite communication is very important. A review of the state-of-the-art PA in the Ka band is presented in this article. The structure of the PA introduced includes common source, cascode, stacked field-effect transistor (FET), power combining, and Doherty PA, highlighting the advantages and disadvantages. The main solid-state technologies are outlined, including Si, SiGe, GaAs, and GaN, emphasizing Si complementary metal–oxide–semiconductor (CMOS) due to low price and high integration.

Investigation on the passivation, band alignment, gate charge, and mobility degradation of the Ge MOSFET with a GeO x /Al2O3 gate stack by ozone oxidation

Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al2O3/GeO x /Ge stack by ozone oxidation is reviewed. The GeO x passivation mechanism by ozone oxidation and band alignment of Al2O3/GeO x /Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.

Room Temperature Ferromagnetism of Monolayer Chromium Telluride with Perpendicular Magnetic Anisotropy.

The realization of long-range magnetic ordering in 2D systems can potentially revolutionize next-generation information technology. Here, the successful fabrication of crystalline Cr3 Te4 monolayers with room temperature (RT) ferromagnetism is reported. Using molecular beam epitaxy, the growth of 2D Cr3 Te4 films with monolayer thickness is demonstrated at low substrate temperatures (≈100 °C), compatible with Si complementary metal oxide semiconductor technology. X-ray magnetic circular dichroism measurements reveal a Curie temperature (Tc ) of v344 K for the Cr3 Te4 monolayer with an out-of-plane magnetic easy axis, which decreases to v240 K for the thicker film (≈7nm) with an in-plane easy axis. The enhancement of ferromagnetic coupling and the magnetic anisotropy transition is ascribed to interfacial effects, in particular the orbital overlap at the monolayer Cr3 Te4 /graphite interface, supported by density-functional theory calculations. This work sheds light on the low-temperature scalable growth of 2D nonlayered materials with RT ferromagnetism for new magnetic and spintronic devices.

Proton radiation hardness of x-ray SOI pixel sensors with pinned depleted diode structure

X-ray silicon-on-insulator (SOI) pixel sensors, “XRPIX,” are being developed for the next-generation x-ray astronomical satellite, “FORCE.” The XRPIX is fabricated with the SOI technology, which makes it possible to integrate a high-resistivity Si sensor and a low-resistivity Si complementary metal oxide semiconductor (CMOS) circuit. The CMOS circuit in each pixel is equipped with a trigger function, allowing us to read out outputs only from the pixels with x-ray signals at the timing of x-ray detection. This function thus realizes high throughput and high time resolution, which enables to employ anti-coincidence technique for background rejection. A new series of XRPIX named XRPIX6E developed with a pinned depleted diode (PDD) structure improves spectral performance by suppressing the interference between the sensor and circuit layers. When semiconductor x-ray sensors are used in space, their spectral performance is generally degraded owing to the radiation damage caused by high-energy protons. Therefore, before using an XRPIX in space, it is necessary to evaluate the extent of degradation of its spectral performance by radiation damage. Thus, we performed a proton irradiation experiment for XRPIX6E for the first time at Heavy Ion Medical Accelerator in Chiba in the National Institute of Radiological Sciences. We irradiated XRPIX6E with high-energy protons with a total dose of up to 40 krad, equivalent to 400 years of irradiation in orbit. The 40-krad irradiation degraded the energy resolution of XRPIX6E by 25 ± 3 % , yielding an energy resolution of 260.1 ± 5.6 eV at the full-width half maximum for 5.9 keV X-rays. However, the value satisfies the requirement for FORCE, 300 eV at 6 keV, even after the irradiation. It was also found that the PDD XRPIX has enhanced radiation hardness compared to previous XRPIX devices. In addition, we investigated the degradation of the energy resolution; it was shown that the degradation would be due to increasing energy-independent components, e.g., readout noise.

Theoretical Prediction of High-Performance Room-Temperature InGaAs/Si Single-Photon Avalanche Diode Fabricated by Semiconductor Interlayer Bonding

Single-photon avalanche diode (SPAD) is an ultrasensitive device for the detection of weak signals. Epitaxial InP-based devices exhibit poor avalanche characteristics and poor compatibility with Si complementary metal oxide semiconductor (CMOS) circuit, and epitaxial Si-based devices show high dark count rate (DCR) and limited detection wavelength. Here we first show a new generation of InGaAs-on-Si SPADs, achieved by semiconductor interlayer bonding, for the detection of 1550-nm infrared signals theoretically. This wafer-bonded InGaAs/Si SPAD has enabled a significant step-change in performance. The dark current of this SPAD is four orders of magnitude lower than that of the epitaxial ones (300 K). High gain-bandwidth-product of 254 and 353 GHz is achieved at the gain of ~ 24 and ~ 36, respectively, for the wafer-bonded SPAD with polycrystalline Si bonding layer at InGaAs/Si bonded interface. In comparison with epitaxial SPADs, the wafer-bonded ones exhibit low DCR ( ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> Hz at 10% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> ), high single photon detection efficiency ( ~ 24% at 10% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> ), and high pulse repetition rate (1 GHz at 5% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> ) at 300 K. These results indicate that utilizing the wafer-bonded platform, the route toward high-performance InGaAs-on-Si SPAD arrays for use in future eye-safe laser radar (LIDAR) and quantum communication at room temperature (RT) is expected to be achieved.

Epitaxial BaTiO3 on Si(100) with In-Plane and Out-of-Plane Polarization Using a Single TiN Transition Layer

The integration of BaTiO3 with Si(100) is essential to exploit its ferroelectric capabilities in the well-established Si-complementary metal–oxide–semiconductor (CMOS) technological platform. To en...

Low‐Power Computing with Neuromorphic Engineering

The increasing power consumption in the existing computation architecture presents grand challenges for the performance and reliability of very‐large‐scale integrated circuits. Inspired by the characteristics of the human brain for processing complicated tasks with low power, neuromorphic computing is intensively investigated for decreasing power consumption and enriching computation functions. Hardware implementation of neuromorphic computing with emerging devices substantially reduces power consumption down to a few mW cm−2, compared with the central processing unit based on conventional Si complementary metal–oxide semiconductor (CMOS) technologies (50–100 W cm−2). Herein, a brief introduction on the characteristics of neuromorphic computing is provided. Then, emerging devices for low‐power neuromorphic computing are overviewed, e.g., resistive random access memory with low power consumption (&lt; pJ) per synaptic event. A few computation models for artificial neural networks (NNs), including spiking neural network (SNN) and deep neural network (DNN), which boost power efficiency by simplifying the computing procedure and minimizing memory access are discussed. A few examples for system‐level demonstration are described, such as mixed synchronous–asynchronous and reconfigurable convolution neuron network (CNN)–recurrent NN (RNN) for low‐power computing.

Ultrasensitive Magnetic Sensors Enabled by Heterogeneous Integration of Graphene Hall Elements and Silicon Processing Circuits.

Graphene Hall elements (GHEs) have been demonstrated to be promising magnetic field sensors with excellent sensitivity, linearity, temperature stability, and compatibility with complementary-metal-oxide-semiconductor (CMOS)-integrated circuits (ICs). However, the demonstrated GHEs have still not exhibited a comprehensive advantage in performance over commercial integrated Hall sensors which were implemented in integrated Hall element and CMOS processing ICs. In this work, we develop a technology for the three-dimensional (3D) heterogeneous integration of silicon-based CMOS ICs and GHEs, and the fabricated magnetic field sensors outperform commercial high-end integrated Hall sensors. Specifically, the integrated Hall sensors are implemented in a stacked integration on Si based on a chopper programmable-gain amplifier (CPGA), a chopper-stabilized second-order sigma-delta modulator (CSDM), and graphene-based Hall elements on monochips. GHEs with high sensitivity (up to 1000 A/VT) are fabricated with a compatible process on a smoothened silicon nitride passivation layer of silicon-based CMOS ICs, and the two device layers are connected by an interlayer. The heterogeneous integrated Hall ICs exhibit current and voltage magnetic sensitivities up to 64 000 A/VT and 6.12 V/VT, respectively, which are much higher than those in all other reported nanomaterial-based Hall sensors and even in high-end commercial Hall ICs. Furthermore, the 3D heterogeneous integration technology used here can be extended as a universal technology for integrating nanomaterial-based sensors and Si CMOS ICs.

Electron-phonon coupling in n -type Ge two-dimensional systems

Electron-optical phonon interaction is the dominant energy-loss mechanism in low-dimensional Ge/SiGe heterostructures and represents a key parameter for the design and realization of electronic and optoelectronic devices based on this material system compatible with the mainstream Si complementary metal-oxide semiconductor technology. Here we investigate the intersubband relaxation dynamics of $n$-type Ge/SiGe multiquantum wells with different symmetry and design by means of single-color pump-probe spectroscopy. By comparing the experimental differential transmittance data as a function of the pump-probe delay with numerical calculations based on an energy-balance rate-equation model, we could quantify an effective value for the optical phonon deformation potential describing the electron-phonon coupling in two-dimensional Ge-based systems. We found nonradiative relaxation times longer than 20 ps even in samples having intersubband energy separations larger than the optical phonon energy, evidencing the presence of a less effective electron-phonon coupling with respect to that estimated in bulk Ge.

Realization of wafer-scale single-crystalline GaN film on CMOS-compatible Si(100) substrate by ion-cutting technique

Heterogeneous integration of gallium nitride (GaN) film on complementary metal-oxide-semiconductor (CMOS)-compatible Si(100) substrate provides a material platform for future high-performance chips with multiple functions. In this work, a 2 inch wafer-scale single-crystalline GaN film is transferred from commercialized bulk GaN wafer onto Si(100) substrate by combining ion-slicing and modified surface-activated bonding with a sputtering-deposited Si nanolayer. The H+ implantation fluence for the exfoliation of GaN film is as low as 2.5 × 1017 cm−2 and the full width at half maximum of the (0002) x-ray rocking curve of GaN film is 203 arcsec. The sliced bulk GaN wafer is recycled, which is beneficial to reduce the cost and to enhance the mass application of the ion-cutting technique to GaN. The exfoliation mechanism of H-implanted GaN is investigated. The activation energy for slicing GaN is only 2.08 eV owing to the high quality of the GaN wafer, while the wide residual damage band is still an obstacle to improving the quality of the GaN film. The successful demonstration of wafer-scale single-crystalline GaN film on Si(100) substrate will be of great benefit to the integration of high-performance GaN devices and Si CMOS integrated circuits with mature processing technology.

GaN-Based LEDs Grown on Graphene-Covered SiO2/Si (100) Substrate

The growth of nitride on large-size and low-cost amorphous substrates has attracted considerable attention for applications in large-scale optoelectronic devices. In this paper, we reported the growth of GaN-based light-emitting diodes (LEDs) on amorphous SiO2 substrate with the use of nanorods and graphene buffer layers by metal organic chemical vapor deposition (MOCVD). The effect of different growth parameters on the morphology and vertical-to-lateral aspect ratio of nanorods was discussed by analyzing growth kinetics. Furthermore, we tuned nanorod coalescence to obtain continuous GaN films with a blue-LED structure by adjusting growth conditions. The GaN films exhibited a hexagonal wurtzite structure and aligned c-axis orientation demonstrated by X-ray diffractometer (XRD), Raman, and transmission electron microscopy (TEM) results. Finally, five-pair InGaN/GaN multi-quantum-wells (MQWs) were grown. The photoluminescence (PL) showed an intense emission peak at 475 nm, and the current–voltage (I-V) curve shows a rectifying behavior with a turn-on voltage of 5.7 V. This work provides a promising fabrication method for the large-area and low-cost GaN-based devices on amorphous substrates and opens up the further possibility of nitride integration with Si (100) complementary metal oxide semiconductor (CMOS) electronics.

Low Temperature Growth of Crystalline Semiconductors on Nonepitaxial Substrates

AbstractIn this work, a low temperature templated liquid phase (LT‐TLP) growth process is presented, that enables one to directly grow high optoelectronic quality single crystalline compound semiconductors (InP and InAs) on amorphous dielectrics at temperatures below 400 °C. Uniquely, the material quality is optimal when InP is grown at 300 °C, a temperature which is low enough to enable back‐end‐of‐line growth on fully fabricated Si complementary metal oxide semiconductor circuits. Using this low‐temperature grown InP, a transistor fabrication process is then entirely carried out at 300 °C or below, and an indium phosphide nanoribbon field effect transistor with excellent on/off ratios is demonstrated, indicating low defect density in the material. Overall, this approach enables growth of large area (tens of micron) single crystal compound semiconductor at low temperatures, establishing a back‐end‐of‐line (BEOL) compatible process for monolithic 3D device integration.

Ag2S QDs/Si Heterostructure-Based Ultrasensitive SWIR Range Detector.

In the 20th century, microelectronics was revolutionized by silicon—its semiconducting properties finally made it possible to reduce the size of electronic components to a few nanometers. The ability to control the semiconducting properties of Si on the nanometer scale promises a breakthrough in the development of Si-based technologies. In this paper, we present the results of our experimental studies of the photovoltaic effect in Ag2S QD/Si heterostructures in the short-wave infrared range. At room temperature, the Ag2S/Si heterostructures offer a noise-equivalent power of 1.1 × 10−10 W/√Hz. The spectral analysis of the photoresponse of the Ag2S/Si heterostructures has made it possible to identify two main mechanisms behind it: the absorption of IR radiation by defects in the crystalline structure of the Ag2S QDs or by quantum QD-induced surface states in Si. This study has demonstrated an effective and low-cost way to create a sensitive room temperature SWIR photodetector which would be compatible with the Si complementary metal oxide semiconductor technology.