Si CMOS Research Articles

Ferroelectricity in Ultrathin HfO2-Based Films by Nanosecond Laser Annealing.

Nonvolatile memory devices based on ferroelectric HfxZr1-xO2 (HZO) show great promise for back-end integrable storage and for neuromorphic accelerators, but their adoption is held back by the inability to scale down the HZO thickness without violating the strict thermal restrictions of the Si CMOS back end of line. In this work, we overcome this challenge and demonstrate the use of nanosecond pulsed laser annealing (NLA) to locally crystallize areas of an ultrathin (3.6 nm) HZO film into the ferroelectric orthorhombic phase. Meanwhile, the heat induced by the pulsed laser is confined to the layers above the Si, allowing for back-end compatible integration. We use a combination of electrical characterization, nanofocused scanning X-ray diffraction (nano-XRD), and synchrotron X-ray photoelectron spectroscopy (SXPS) to gain a comprehensive view of the change in material and interface properties by systematically varying both laser energy and the number of laser pulses on the same sample. We find that NLA can provide remanent polarization up to 2Pr= 11.6 μC/cm2 in 3.6 nm HZO, albeit with a significant wake-up effect. The improved TiN/HZO interface observed by XPS explains why device endurance goes beyond 107 cycles, whereas an identical film processed by rapid thermal processing (RTP) breaks already after 106 cycles. All in all, NLA provides a promising approach to scale down the ferroelectric oxide thickness for emerging HZO ferroelectric devices, which is key for their integration in scaled process nodes.

Unconventional magnetoresistance and resistivity scaling in amorphous CoSi thin films

The resistivity scaling of Cu electrical interconnects represents a critical challenge in Si CMOS technology. As interconnect dimensions reach below 10 nm, Cu resistivity increases significantly due to surface scattering. Topological materials have been considered for application in ultra-scaled interconnects (below 5 nm), due to their topologically protected surface states that have reduced electron scattering. Recent theoretical work on the topological chiral semimetal CoSi suggests that this material could offer lower resistivity than Cu at dimensions smaller than 10 nm. Here we investigate the scaling trend of textured and amorphous CoSi thin films, deposited by molecular beam epitaxy in a thickness range between 2 and 82.5 nm. Contrary to predictions of standard resistivity models, we report here a reduction in resistivity for thin amorphous CoSi films, which is instead consistent with surface-dominated transport. Moreover, magnetotransport measurements reveal significant enhancement of the magnetoresistance in scaled films, highlighting the complex transport mechanisms present in these highly disordered films at thicknesses of a few nanometers.

Comparison of Si CMOS and SiC CMOS Operational Amplifiers

In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

SiC MOSFET Gate Oxide Quality Improvement Method in Furnace Thermal Oxidation with Lower Pressure Control

We have investigated carbon behavior resulting from pressure control in furnace thermal oxidation process and evaluated the effect on gate oxide quality resulting from this pressure control. In order to investigate the potential reduction of carbon defects by reducing CO and CO2, an analysis of oxidized SiC wafers was conducted. To evaluate the effect of pressure control related carbon component change during thermal oxidation, QBD characteristic was evaluated in SiC MOS Capacitance. The analysis results revealed on observable decrease in carbon at the SiO2/SiC interface and the SiO2 layer. The QBD results shown that improved at lower pressure better than those obtained in the general pressure.

Dependence of the incorporated boron concentration near SiO2/4H–SiC interface on trap passivation reduction

By systematically varying the boron concentration near the oxide/4H–SiC interface within a specifically designed boron-diffusion layer oxide structure, this paper explores the influence of boron concentration on interface state density and near-interface trap density in 4H–SiC MOS capacitors. Additionally, the effect of boron near the oxide/4H–SiC interface on device stability under elevated temperature conditions was examined. The boron species were introduced into the SiO2/4H–SiC interface by spin coating followed by annealing, whose temperature controls the amount of boron present in the near interface region. It is suggested that a higher concentration of boron leads to a better trap passivation effect while preserving the stability of flat band voltage.

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

A 6 Mbps 7 pJ/bit CMOS Integrated Wireless Simultaneous Lightwave Information and Power Transfer System for Biomedical Implants

A 6 Mbps 7 pJ/bit CMOS Integrated Wireless Simultaneous Lightwave Information and Power Transfer System for Biomedical Implants

Origin and Recovery of Negative VTH Shift on 4H–SiC MOS Capacitors: An Analysis Based on Inverse Laplace Transform and Temperature-Dependent Measurements

SiC power MOSFETs are reported to suffer from both positive and negative threshold voltage shifts. Positive shift is well understood in the literature and attributed to electron trapping in near interface oxide traps (NIOTs). Negative shift is explained by hole generation and trapping in the oxide via impact ionization favored by the strong oxide field. However, studies on negative shift are still ongoing, and the origin and nature of the process are not fully understood. This study advances the comprehension of negative threshold voltage shift by investigating MOS capacitors subject to positive bias stress.We demonstrate that: a) a significant negative threshold shift is observed when the electric field is greater than 7.5 MV/cm; b) the detected shift is not recoverable at zero bias. Recovery can be obtained only by applying a positive gate voltage indicating a field-driven detrapping process. c) Trap-state mapping measurements were carried out to extract the activation energy of the detrapping processes, and a weak thermal activation was observed.Results collected within this paper indicate that holes are trapped at deep centers, and thermal detrapping is not possible. Hole release is only possible when a high field is applied to the insulator, possibly due to the recombination between leaking electrons and trapped holes.

Enhanced Photogating Gain in Scalable MoS2 Plasmonic Photodetectors via Resonant Plasmonic Metasurfaces.

Absorption of photons in atomically thin materials has become a challenge in the realization of ultrathin, high-performance optoelectronics. While numerous schemes have been used to enhance absorption in 2D semiconductors, such enhanced device performance in scalable monolayer photodetectors remains unattained. Here, we demonstrate wafer-scale integration of monolayer single-crystal MoS2 photodetectors with a nitride-based resonant plasmonic metasurface to achieve a high detectivity of 2.58 × 1012 Jones with a record-low dark current of 8 pA and long-term stability over 40 days. Upon comparison with control devices, we observe an overall enhancement factor of >100; this can be attributed to the local strong EM field enhanced photogating effect by the resonant plasmonic metasurface. Considering the compatibility of 2D semiconductors and hafnium nitride with the Si CMOS process and their scalability across wafer sizes, our results facilitate the smooth incorporation of 2D semiconductor-based photodetectors into the fields of imaging, sensing, and optical communication applications.

Chiral anomaly and Weyl orbit in three-dimensional Dirac semimetal Cd3As2 grown on Si

Preparing Cd3As2, which is a three-dimensional (3D) Dirac semimetal in certain crystal orientation, on Si is highly desirable as such a sample may well be fully compatible with existing Si CMOS technology. However, there is a dearth of such a study regarding Cd3As2 films grown on Si showing the chiral anomaly. Here, for the first time, we report the novel preparation and fabrication technique of a Cd3As2 (112) film on a Si (111) substrate with a ZnTe (111) buffer layer which explicitly shows the chiral anomaly with a nontrivial Berry’s phase of π. Despite the Hall carrier density ( n3D≈ 9.42×1017 cm−3) of our Cd3As2 film, which is almost beyond the limit for the portents of a 3D Dirac semimetal to emerge, we observe large linear magnetoresistance in a perpendicular magnetic field and negative magnetoresistance in a parallel magnetic field. These results clearly demonstrate the chiral magnetic effect and 3D Dirac semimetallic behavior in our silicon-based Cd3As2 film. Our tailoring growth of Cd3As2 on a conventional substrate such as Si keeps the sample quality, while also achieving a low carrier concentration.

Lowering of interface state density between deposited gate oxide and SiC substrate via controlling substrate oxidation

The quality of oxide/semiconductor interface in SiC gate stacks is engineered by employing atomic layer deposition of gate oxide and controlling post-deposition annealing (PDA) under the vacuum. We find that the interface state density (Dit) can be substantially lowered by reducing the thickness of thermally formed SiO2 between the deposited gate dielectric and SiC in PDA. In addition, Dit slightly far from the conduction band is further reduced by avoiding low temperature SiC oxidation and that near the conduction band is reduced by controlling suboxide formation. These results provide new insights into improving the interface performance of SiC MOS devices.

Ultra-fast generator for impact ionization triggering

In recent years, it has been discovered that thyristors triggered in impact ionization mode find their dI/dt capability boosted by up to three orders of magnitude. This innovative triggering requires applying an important overvoltage on the anode-cathode of the thyristor with a slew rate > 1 kV/ns. Compact pulse generators based on commercial off the shelf components (COTS) would allow the spread of this technology into numerous applications, including fast kicker generators for particle accelerators.Our approach for such a compact pulse generator begins with a HV SiC MOS with an ultra-fast super-boosting gate driver. Super boosting in the gate of a 1.7 kV rated SiC MOS allows to reduce its rise time by a factor of ≈ 30 (datasheet tr = 20 ns vs. measured tr < 680 ps), resulting in an output voltage slew rate > 1 kV/ns and an amplitude > 1 kV.Next, additional boosting is obtained by a Marx generator with D2PAK thyristors, reaching an output voltage slew rate > 16 kV/ns. Finally, creating sufficient current necessary for the triggering of a big thyristor presents a new challenge. In this paper, we present an upgraded board design with a higher current output capacity.

OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers

OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects.By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors.In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers.A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistorsFully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices.3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type.3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.

High-performance thin-film transistors based on aligned carbon nanotubes for mini- and micro-LED displays

Inorganic mini-LEDs (mLEDs) and micro-LEDs (μLEDs) have ultrahigh luminance and long lifetimes, and are challenging liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays for next-generation displays. Backplane thin-film transistors (TFTs) for mLED/μLED displays with high mobility and large driving current are under development as currently widely used backplane active materials such as crystalline silicon (CMOS Si), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and metal oxides are facing difficulties to meet the requirements. Semiconducting carbon nanotubes (s-CNTs) have long been considered as promising materials for TFTs because of their unique electronic properties. However, TFTs based on s-CNT random networks show inadequate performance due to large amounts of inter-tube junctions. Here, we report high performance TFTs based on wafer-scale, high-density aligned s-CNT array (A-CNT) for mLED/μLED driving backplanes. These A-CNT TFTs with micrometer scale channel length were fabricated using standard semiconductor manufacturing process, and exhibited mobility as high as 160 cm2/Vs and driving current as large as 417 μA/μm at operation voltage of ∼3 V, exceeding commercially available TFTs with similar device sizes. In addition, these A-CNT TFTs have demonstrated good driving capability for commercial mLEDs in a one-transistor-one-diode (1T1D) pixel circuit configuration, and been capable of driving commercially available mLED/μLED displays. Moreover, a prototype display with 2 × 2 mLED array have been demonstrated with full control of each pixel, manifesting the great potential for A-CNT TFT technology for backplane of mLED/μLED displays.

Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration

Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration

CMOS-Compatible Ultrathin Superconducting NbN Thin Films Deposited by Reactive Ion Sputtering on 300 mm Si Wafer

We report a milestone in achieving large-scale, ultrathin (~5 nm) superconducting NbN thin films on 300 mm Si wafers using a high-volume manufacturing (HVM) industrial physical vapor deposition (PVD) system. The NbN thin films possess remarkable structural uniformity and consistently high superconducting quality across the entire 300 mm Si wafer, by incorporating an AlN buffer layer. High-resolution X-ray diffraction and transmission electron microscopy analyses unveiled enhanced crystallinity of (111)-oriented δ-phase NbN with the AlN buffer layer. Notably, NbN films deposited on AlN-buffered Si substrates exhibited a significantly elevated superconducting critical temperature (~2 K higher for the 10 nm NbN) and a higher upper critical magnetic field or Hc2 (34.06 T boost in Hc2 for the 50 nm NbN) in comparison with those without AlN. These findings present a promising pathway for the integration of quantum-grade superconducting NbN films with the existing 300 mm CMOS Si platform for quantum information applications.

600-GHz Fourier imaging based on heterodyne detection at the 2nd sub-harmonic.

Fourier imaging is an indirect imaging method which records the diffraction pattern of the object scene coherently in the focal plane of the imaging system and reconstructs the image using computational resources. The spatial resolution, which can be reached, depends on one hand on the wavelength of the radiation, but also on the capability to measure - in the focal plane - Fourier components with high spatial wave-vectors. This leads to a conflicting situation at THz frequencies, because choosing a shorter wavelength for better resolution usually comes at the cost of less radiation power, concomitant with a loss of dynamic range, which limits the detection of higher Fourier components. Here, aiming at maintaining a high dynamic range and limiting the system costs, we adopt heterodyne detection at the 2nd sub-harmonic, working with continuous-wave (CW) radiation for object illumination at 600 GHz and local-oscillator (LO) radiation at 300 GHz. The detector is a single-pixel broad-band Si CMOS TeraFET equipped with substrate lenses on both the front- and backside for separate in-coupling of the waves. The entire scene is illuminated by the object wave, and the Fourier spectrum is recorded by raster scanning of the single-detector unit through the focal plane. With only 56 µW of power of the 600-GHz radiation, a dynamic range of 60 dB is reached, sufficient to detect the entire accessible Fourier space spectrum in the test measurements. We present a detailed comparison between plane-to-plane imaging and Fourier imaging, and show that, with both, a lateral spatial resolution of better than 0.5 mm, at the diffraction limit, is reached.

Investigation of dynamic ron stability and hot electrons reliability in normally-off AlGaN/GaN power HEMTs

The current collapse and hot electron effect of 100 V normally-off GaN power HEMTs are investigated. The 100 V GaN-on-Si power HEMTs are fabricated on an industrial 200 mm Si CMOS compatible technology platform. The double pulse test (DPT) and the dynamic high temperature operating life (DHTOL) test are implemented to verify the dynamic on-resistance (dynamic Ron) stability. Wafer level hot electron reliability test is performed to investigate the effect of high electric field and high current on GaN power HEMT. It is proved that the dynamic Ron stability of 100 V GaN power HEMT is qualified (Ron/Rini, static < 1.2) when the drain-source off-state voltage (Vdsoff) is less than 80 V. It is shown that the dynamic Ron degradation of GaN device is recoverable by means of annealing. Hot electrons reliability is dominated by the high electric field at drain edge and the high current which is source injected electrons flowing to the drain. It is demonstrated that the Vth drift and Ron degradation are extraordinary serious under semi on-state stress condition with Vdsoff = 60 V.