Si CMOS Technology Research Articles

Unconventional magnetoresistance and resistivity scaling in amorphous CoSi thin films

The resistivity scaling of Cu electrical interconnects represents a critical challenge in Si CMOS technology. As interconnect dimensions reach below 10 nm, Cu resistivity increases significantly due to surface scattering. Topological materials have been considered for application in ultra-scaled interconnects (below 5 nm), due to their topologically protected surface states that have reduced electron scattering. Recent theoretical work on the topological chiral semimetal CoSi suggests that this material could offer lower resistivity than Cu at dimensions smaller than 10 nm. Here we investigate the scaling trend of textured and amorphous CoSi thin films, deposited by molecular beam epitaxy in a thickness range between 2 and 82.5 nm. Contrary to predictions of standard resistivity models, we report here a reduction in resistivity for thin amorphous CoSi films, which is instead consistent with surface-dominated transport. Moreover, magnetotransport measurements reveal significant enhancement of the magnetoresistance in scaled films, highlighting the complex transport mechanisms present in these highly disordered films at thicknesses of a few nanometers.

Chiral anomaly and Weyl orbit in three-dimensional Dirac semimetal Cd3As2 grown on Si

Preparing Cd3As2, which is a three-dimensional (3D) Dirac semimetal in certain crystal orientation, on Si is highly desirable as such a sample may well be fully compatible with existing Si CMOS technology. However, there is a dearth of such a study regarding Cd3As2 films grown on Si showing the chiral anomaly. Here, for the first time, we report the novel preparation and fabrication technique of a Cd3As2 (112) film on a Si (111) substrate with a ZnTe (111) buffer layer which explicitly shows the chiral anomaly with a nontrivial Berry’s phase of π. Despite the Hall carrier density ( n3D≈ 9.42×1017 cm−3) of our Cd3As2 film, which is almost beyond the limit for the portents of a 3D Dirac semimetal to emerge, we observe large linear magnetoresistance in a perpendicular magnetic field and negative magnetoresistance in a parallel magnetic field. These results clearly demonstrate the chiral magnetic effect and 3D Dirac semimetallic behavior in our silicon-based Cd3As2 film. Our tailoring growth of Cd3As2 on a conventional substrate such as Si keeps the sample quality, while also achieving a low carrier concentration.

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects.By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors.In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers.A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistorsFully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices.3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type.3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

To keep the scaling progress going, we must go three dimensional (3D). This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connecting them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature than today’s Si CMOS technology. Here, we have focused on Ge based transistors, which have an inherently lower process temperature compared to Si transistors. Several technological and design breakthroughs towards realizing Ge based sequential 3D circuits are discussed.

Synthesis of Large-Area Crystalline MoS2 by Sputter Deposition and Pulsed Laser Annealing

The wafer-scale synthesis of layered transitional metal dichalcogenides presenting good crystal quality and homogeneous coverage is a challenge for the development of next-generation electronic devices. This work explores a fairly unconventional growth method based on a two-step process consisting in sputter deposition of stochiometric MoS2 on Si/SiO2 substrates followed by nanosecond UV (248 nm) pulsed laser annealing. Large-scale 2H-MoS2 multi-layer films were successfully synthetized in a N2-rich atmosphere thanks to a fine-tuning of the laser annealing parameters by varying the number of laser pulses and their energy density. The identification of the optimal process led to the success in achieving a (002)-oriented nanocrystalline MoS2 film without performing post-sulfurization. It is noteworthy that the spatial and temporal confinement of laser annealing keeps the Si/SiO2 substrate temperature well below the back-end-of-line temperature limit of Si CMOS technology (770 K). The synthesis method described here can speed up the integration of large-area 2D materials with Si-based devices, paving the way for many important applications.

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation.

2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe2 ) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe2 FETs has been switched from hole to electron. The ultrathin body of WSe2 , combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. Theunique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.

Insights on the variability of Cu filament formation in the SiO2 electrolyte of quantized-conductance conductive bridge random access memory devices

Conductive bridge random access memory devices such as Cu/SiO2/W are promising candidates for applications in neuromorphic computing due to their fast, low-voltage switching, multiple-conductance states, scalability, low off-current, and full compatibility with advanced Si CMOS technologies. The conductance states, which can be quantized, originate from the formation of a Cu filament in the SiO2 electrolyte due to cation-migration-based electrochemical processes. A major challenge related to the filamentary nature is the strong variability of the voltage required to switch the device to its conducting state. Here, based on a statistical analysis of more than hundred fifty Cu/SiO2/W devices, we point to the key role of the activation energy distribution for copper ion diffusion in the amorphous SiO2. The cycle-to-cycle variability is modeled well when considering the theoretical energy landscape for Cu diffusion paths to grow the filament. Perspectives of this work point to developing strategies to narrow the distribution of activation energies in amorphous SiO2.

Tuning the interlayer microstructure and residual stress of buffer-free direct bonding GaN/Si heterostructures

The direct integration of GaN with Si can boost great potential for low-cost, large-scale, and high-power device applications. However, it is still challengeable to directly grow GaN on Si without using thick strain relief buffer layers due to their large lattice and thermal-expansion-coefficient mismatches. In this work, a GaN/Si heterointerface without any buffer layer is fabricated at room temperature via surface activated bonding (SAB). The residual stress states and interfacial microstructures of GaN/Si heterostructures were systematically investigated through micro-Raman spectroscopy and transmission electron microscopy. Compared to the large compressive stress that existed in GaN layers grown on Si by metalorganic chemical vapor deposition, a significantly relaxed and uniform small tensile stress was observed in GaN layers bonded to Si by SAB; this is mainly ascribed to the amorphous layer formed at the bonding interface. In addition, the interfacial microstructure and stress states of bonded GaN/Si heterointerfaces was found to be significantly tuned by appropriate thermal annealing. With increasing annealing temperature, the amorphous interlayer formed at the as-bonded interface gradually transforms into a thin crystallized interlayer without any observable defects even after annealing at 1000 °C, while the interlayer stresses at both GaN layer and Si monotonically change due to the interfacial re-crystallization. This work moves an important step forward directly integrating GaN to the present Si CMOS technology with high quality thin interfaces and brings great promises for wafer-scale low-cost fabrication of GaN electronics.

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

Si-CMOS-compatible 2D PtSe2-based self-driven photodetector with ultrahigh responsivity and specific detectivity

Photodetectors (PDs) based on two-dimensional (2D) materials are attracting considerable research interest due to the unique properties of 2D materials and their tunable spectral response. However, their performance is not outstanding enough, and the compatibility of their fabrication process with Si-complementary metal oxide semiconductor (CMOS) process flow needs evaluation. Here, we report an unprecedented high-performance, air-stable, self-driven, and broadband room-temperature PD based on the architecture of the PtSe2/ultrathin SiO2/Si heterojunction. The PD exhibits a very prominent responsivity of 8.06 A W−1, a truly high specific detectivity of 4.78 × 1013 cm Hz1/2 W−1, an extremely low dark current of 0.12 pA, and a fantastic photocurrent/dark current ratio of 1.29 × 109 at zero bias. The measured photocurrent responsivities at wavelengths of 375, 532, 1342, and 1550 nm are 2.12, 5.56, 18.12, and 0.65 mA W−1, respectively. Moreover, the fabricated 9 × 9 device array not only illustrates the very high uniformity and reproducibility of the PDs but also shows great potential in the field of ultraviolet-visiblenear infrared illumination imaging applications with a fabrication fully compatible with Si-CMOS technologies. Our design of the PtSe2/ultrathin SiO2/Si heterojunction PD greatly suppresses dark current, improves the diode ideality factor, and increases the potential barrier. Accordingly, it paves the way for a general strategy to enhance the performance of PDs used in novel optoelectronic applications.

200 mm-scale growth of 2D layered GaSe with preferential orientation

In this article, we present a fab-compatible metal–organic chemical vapor deposition growth process, realized in a hydrogen ambience, of two-dimensional (2D) layered GaSe on 200 mm diameter Si(111) wafers. Atomic scale characterization reveals initial stages of growth consisting of passivation of the H–Si (111) surface by a half-monolayer of GaSe, followed by nucleation of 2D-GaSe from the screw dislocations located at the step edges of the substrate. We, thus, demonstrate that by using a Si wafer that is slightly misoriented toward [1̄1̄2], the crystallographic orientation of 2D-GaSe can be step-edge-guided. It results in a coalesced layer that is nearly free from antiphase boundaries. In addition, we propose a sequential process to reduce the density of screw dislocations. This process consists in a subsequent regrowth after partial sublimation of the initially grown GaSe film. The local band bending in GaSe near the antiphase boundaries measured by Kelvin probe force microscopy emphasizes the electrical activity of these defects and the usefulness of having a nearly single-orientation film. Such a low defectivity layer opens up the way toward large-scale integration of 2D-optical transceivers in Si CMOS technology.

IEEE Open Journal of the Solid-State Circuits Society Special Section on Integrated Circuits and Systems Based on Thin-Film Transistors

Thin-Film transistors (TFTs) are ubiquitous today as a backplane technology for various display and imager products. Those transistors act as switches in active-matrix liquid-crystal displays (AM-LCDs) or as full-pixel engines, including driving and threshold compensation, in active-matrix organic light-emitting diodes (AM-OLEDs) panels. TFT manufacturing requires only a limited amount of photolithographic steps, making it a relatively simple transistor technology, compared to the traditional Si CMOS technologies. The processing temperature of TFT technologies is sufficiently low to be compatible with glass and can even enable flexible substrates. Finally, these transistors have been developed specifically for large-area applications, such as televisions and X-ray scanners. Consequently, the backplane size for TFTs has evolved from the generation-1 glass panel of 270 mm by 360 mm to generation-10.5, which is manufactured on a glass panel of 2.94 m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times3.37$ </tex-math></inline-formula> m <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> . This is profoundly different from traditional Si CMOS integrated circuits, which are fabricated nowadays on 200 mm or 300 mm round wafers. The critical dimension of the TFT technology on glass or flexible substrate in production is in the range of a few micrometers. The TFT research in the display field focuses on enabling increasingly better pixel resolution, improved visual quality, larger panels for LED walls, flexible displays, camera-behind display, sensor integration, and many more.

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices. Owing to the 3D wrapped gate structure, MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region. As the Si CMOS technology pioneers to sub-10 nm nodes, the process challenges in terms of lithography capability, process integration controversies, performance variability etc. were also discussed in this work. Due to the severe self-heating effect in the MuGFETs, the ballistic transport and reliability characteristics were investigated. Future alternatives for the current Si MuGFET technology were discussed at the end of the paper. More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.

Mobility enhancement techniques for Ge and GeSn MOSFETs

The performance enhancement of conventional Si MOSFETs through device scaling is becoming increasingly difficult. The application of high mobility channel materials is one of the most promising solutions to overcome the bottleneck. The Ge and GeSn channels attract a lot of interest as the alternative channel materials, not only because of the high carrier mobility but also the superior compatibility with typical Si CMOS technology. In this paper, the recent progress of high mobility Ge and GeSn MOSFETs has been investigated, providing feasible approaches to improve the performance of Ge and GeSn devices for future CMOS technologies.

B and Ga Co-Doping in Epitaxial SiGe: Challenges and Opportunities

Contact resistances are inherent to any device connected to the outside world. Lowering their contribution is essential for high-performance applications. This is the case for advanced Si CMOS technologies, for which series resistance parasitics become the main performance detractor from the 14 nm node onwards [1-2]. For p-type fin and gate-all-around field effect transistors, focus is placed on Ti contacts to p-Si1-xGex source/drain (S/D) [3].Several non-equilibrium doping techniques have been explored to enhance active doping in S/D regions and decrease contact resistivities (ρc) down to ≤ 1x10-9 Ω.cm2. In most cases, low temperature doping processes are used to favor the incorporation of dopants and their activation [4]. Alternative dopants, with higher solid solubilities and advantageous segregation behaviors favoring the formation of dopant-enriched films at the metal-semiconductor interface, are also evaluated. Very low ρc values have e.g. been reported by combining Ga ion implantation in Si0.4Ge0.6 and ns laser annealing [5]; whereas in situ doping was optimized in Si1-xGex:B [6-9] and Si0.5Ge0.5:B:Ga, grown by chemical vapor deposition using metalorganic (MO) Ga precursors [4,10]. In this contribution, we highlight opportunities and challenges offered by this approach.The maximum solubility of Ga in Ge is more than 100x higher than that of B [11-12]. However, controlling the incorporation and distribution of Ga dopants in Si0.5Ge0.5(:B) is not straightforward. This relates to the tendency for Ga to segregate towards the surface, as reported in [4,10] and shown in Fig. 1(a). We rely on Si0.5Ge0.5:B:Ga co-doped epi layers in which bulk resistivity is lowered thanks to high B-doping concentrations, while contact resistivity minimization is expected from Ga segregation towards the contact region. It appears, however, that Ga surface doping concentrations significantly higher than 3E20 cm-3 are required to efficiently reduce ρc [5,13]. Targeting such high surface concentrations comes with the risk of Ga agglomeration into Ga-rich defects on S/D surfaces. Another detractor lies in the possible consumption of superficial Ga during native oxide removal preceding contact processing. Results presented in Fig. 1(b) suggest such a ~ 10x decrease in Ga concentration close to the S/D surface after native oxide removal. Systematic investigations are underway to clarify this aspect, which could lead us to reconsider our contacting scheme.Activating high levels of Ga dopants in in situ doped epi layers is an additional challenge. Preliminary results indicate that, in the conditions explored in this work, only a small fraction of the dopants incorporated in SiGe:Ga are active. This limitation may be attributed to Ga dopants clustering or to interactions with unwanted C incorporated during growth. Fig. 1(c) illustrates our effort in reducing C incorporation in SiGe:B:Ga by utilizing 2 different Ga MO precursors, namely MO1 and MO2, while keeping all other growth parameters the same. For this test, an undoped SiGe cap was used to separate contributions from adventitious C and C really incorporated in the SiGe:B:Ga layer. Ga profiles appear to be affected by the capping, with part of the Ga dopants migrating towards the top part of the stack. C impurities are on the other hand assumed to be frozen in their original position [14]. While the level of incorporated C is not significantly affected by the choice of precursor, a shorter Ga incorporation delay, materialized by blue arrows in Fig. 1(c), and a larger [Ga] / [C] ratio are extracted from the layer grown with MO2.

Manifestation of the channeling effect when manufacturing JFET transistors

TThe proposed work covers the tasks of such areas as reducing input currents and bias voltage of integrated operational amplifiers (ICs OA) manufactured according to BiFET technology, the prospect of using JFET transistors in digital circuit technology, Si CMOS technology at 22 nm node and beyond, manufacturing bipolar transistors on ultra-thin layers of the active base and emitter, increasing resistance of ICs to external influences. The main method of experimental investigation of channeling is the construction of impurity distribution profiles using SIMS. In this work to study the channeling effect of boron and phosphorus in silicon was chosen the method for constructing the response surface of the saturation current of JFET for a silicon wafer. The choice of method was based on the high sensitivity of the cut-off voltage and saturation current of the JFET transistor to the channel thickness and impurity concentration in it, the relative simplicity of performance and practical benefits in improving BiFET technology.

(Invited) How Far Can We Push Conventional Silicon Technology and What are the Future Alternatives?

Si CMOS technology has dominated the microelectronics industry, with continued scaling. However, future scaling is reaching practical and fundamental limits. Currently, strained-Si channel with high-k/metal gate is the dominant technology. Si FinFETs have provided further innovation to improve electrostatic control of the channel and thus reduce leakage. However, performance enhancement of Si CMOS is beginning to saturate with scaling to nanoscale. To go beyond these limits novel materials and structures are being aggressively studied. Higher mobility semiconductors, like Ge, GeSn and III-Vs, together with innovative device structures could increase drive current and reduce power consumption and delay. Carbon nanotubes and graphene offer very high mobility, excellent electrostatic control of the channel but have problems in manufacturability. Graphene also has the problem of ~0 bandgap making it not very useful for logic. Recently 2D materials like metal sulfides, telurides and selenides have emerged as potential candidates for nanoscale devices.Is Ge PMOS and III-V NMOS co-integration on Si feasible or a headache for the manufacturing folks? Can we have all Ge or all III-V CMOS or it is just a fantasy? Can CNT FETs become manufacturable? Are 2D materials more promising? This talk will try to answer some of these questions.

Up to 70 THz bandwidth from an implanted Ge photoconductive antenna excited by a femtosecond Er:fibre laser

Phase-stable electromagnetic pulses in the THz frequency range offer several unique capabilities in time-resolved spectroscopy. However, the diversity of their application is limited by the covered spectral bandwidth. In particular, the upper frequency limit of photoconductive emitters - the most widespread technique in THz spectroscopy – reaches only up to 7 THz in the regular transmission mode due to absorption by infrared-active optical phonons. Here, we present ultrabroadband (extending up to 70 THz) THz emission from an Au-implanted Ge emitter that is compatible with mode-locked fibre lasers operating at wavelengths of 1.1 and 1.55 μm with pulse repetition rates of 10 and 20 MHz, respectively. This result opens up the possibility for the development of compact THz photonic devices operating up to multi-THz frequencies that are compatible with Si CMOS technology.

A 300-GHz CMOS 7-by-7 Detector Array for Optics-less THz Imaging with Scan-less Target Object

In this work, a 300-GHz 7 × 7 detector array based on a 65-nm Si CMOS technology has been developed and transmission imaging was performed using the detector array without any optical elements. The detector array consists of a 7-by-7 arrangement of 49 pixels in a full-chip size of 4 mm × 4 mm. The unit pixel is composed of a single direct detector with a differential common-gate configuration and a differential patch antenna. The fabricated CMOS detector array chip was mounted on a planar package for electrical characterization and imaging. The measured responsivity and the noise equivalent power (NEP) showed best values of 3599 V/W and 12.46 pW/Hz1/2, respectively, at 303 GHz. Various THz imaging experiments were carried out based on the packaged CMOS detector array with a setup that does not require optical elements or the raster scan of the target object.

Millimeter-Wave Noise Source Development on SiGe BiCMOS 55-nm Technology for Applications up to 260 GHz

This paper describes the development and characterization of a millimeter-wave (mmW) integrated noise source development on silicon technology for applications up to 260 GHz. The developed integrated noise source is based on p-n and Schottky junction in series, realized on the SiGe BiCMOS 55-nm technology from STMicroelectronics. Biased in the avalanche regime, this integrated diode noise source achieves a tunable excess noise ratio (ENR) ranged between 0 dB and 15 dB, in the 130–260-GHz frequency range. In order to highlight the usefulness of the integrated noise source, the noise figure of two amplifiers was measured: the first one is an integrated low-noise amplifier (LNA) operating in the D-band (130–170 GHz) while the second one is packaged and operates from 220 to 260 GHz. Due to its ability to be naturally integrated on silicon, this noise source features a strong interest to carry out high-frequency in situ noise characterization of advanced Si CMOS or BiCMOS technologies in the mmW range.