Si CMOS Platform Research Articles

Van der Waals Layer Transfer of 2D Materials for Monolithic 3D Electronic System Integration: Review and Outlook.

Two-dimensional materials (2DMs) have attracted a great deal of interest due to their immense potential for scientific breakthroughs and technological innovations. While some 2D transition metal dichalcogenides (TMDC) such as MoS2 and WS2 are considered as the ultimate channel materials in unltrascaled transistors as replacements for Si, there has also been increasing interest in the monolithic 3D integration of 2DMs on the Si CMOS platform or in flexible electronics as back-end-of-line transistors, memory devices/selectors, and sensors, taking advantage of 2DM properties such as a high current driving capability with low leakage current, nonvolatile switching characteristics, a large surface-to-volume ratio, and a tunable bandgap. However, the realization of both of these scenarios critically depends on the development of manufacturing-viable high-yield 2DM layers transfer from the growth substrate to the Si, since the growth of high-quality 2DM layers often requires a high-temperature growth process on template substrates. Motivated by this, extensive efforts have been made by the 2DM research community to develop various 2DM layer transfer methods, leveraging the van der Waals transfer capability of the layer-structured 2DMs. These efforts have led to a number of successful demonstrations of wafer-scale 2D TMDC layer transfer, while 2DM-enabled template growth/transfer of some functional bulk materials such as III-V, Ge, and AlN has also been demonstrated. This review surveys and compares different 2DM transfer methods developed recently, with a focus on large-area 2D TMDC film transfer along with an introduction of 2DM template-assisted van der Waals growth/transfer of non-2D thin films. We will also briefly present an outlook of our envisioned multifunctionalities in 3D integrated electronic systems enabled by monolithic 3D integration of 2DMs and III-V via van der Waals transfer and discuss possible technology options for overcoming remaining challenges.

Cavity-enhanced InGaAs photo-FET with a metal gate reflector fabricated by wafer bonding on Si

Although an InGaAs photo field-effect transistor (photo-FET) is a promising solution for high-performance photodetector due to its internal gain mechanism, the reported opto-electrical performance is limited by the low absorption caused by its thin body thickness and unoptimized electrical properties. To overcome this limitation, an InGaAs photo-FET with a metal gate reflector was demonstrated to achieve both high electrical and optical performance. We designed and optimized a metal-oxide-semiconductor (MOS) structure with the metal gate reflector by using numerical calculation and process optimization. Thanks to the optimization of both electrical and optical characteristics, the InGaAs photo-FETs were successfully demonstrated at the wavelengths of 1305 nm and 1550 nm. Therefore, this wafer-bonded InGaAs photo-FET with the metal gate reflector is a promising candidate for a high-performance and broad-band SWIR photodetector on a Si CMOS platform.

Fabrication of All-GaN Integrated MIS-HEMTs with High Threshold Voltage Stability Using Supercritical Technology.

In this paper, a novel method to achieve all-GaN integrated MIS-HEMTs in a Si-CMOS platform by self-terminated and self-alignment process is reported. Furthermore, a process of repairing interface defects by supercritical technology is proposed to suppress the threshold voltage shift of all GaN integrated MIS-HEMTs. The threshold voltage characteristics of all-GaN integrated MIS-HEMTs are simulated and analyzed. We found that supercritical NH fluid has the characteristics of both liquid NH and gaseous NH simultaneously, i.e., high penetration and high solubility, which penetrate the packaging of MIS-HEMTs. In addition, NH produced via the auto coupling ionization of NH has strong nucleophilic ability, and is able to fill nitrogen vacancies near the GaN surface created by high temperature process. The fabricated device delivers a threshold voltage of 2.67 V. After supercritical fluid treatment, the threshold voltage shift is reduced from 0.67 V to 0.13 V. Our demonstration of the supercritical technology to repair defects of wide-bandgap family of semiconductors may bring about great changes in the field of device fabrication.

Towards Ultra-Low Specific Contact Resistance on P-Type and N-Type Narrow Bandgap GeSn Semiconductors

GeSn alloys are group IV semiconductors that have attracted remarkable interest owing to their ability of strain and bandgap engineering by controlling the Sn content, their compatibility with the Si CMOS platform and their tunable and direct band gap. These material properties make GeSn a promising candidate for many electronic and optoelectronic applications including among others tunnel field effect transistors, infrared (IR) photodectors, and IR emitters. However, in order to produce high quality GeSn devices to enable these applications, it is of paramount importance to develop ohmic metal contacts with very low specific contact resistivity on both n-type and p-type doped GeSn layers used in these devices. This could be achieved by realizing high doping levels and attaining low intrinsic barrier heights between the metal and the contacted GeSn layer.The growth of metastable GeSn semiconductors is typically performed at temperatures well below 400 ºC to avoid Sn segregation and phase separation, which would compromise the opto-electronic properties of the material. [1] Therefore, major care is required when developing post-growth processes that are commonly required for device fabrication. For instance, ohmic contact formation using the conventional process of rapid thermal annealing of nickel contacts cannot be made and the GeSn cannot be cured after dopant implantation because of the very limited thermal budget. We investigated both the epitaxial growth of highly doped layers, as well as the passivation of undoped GeSn samples in order to circumvent these limitations and achieve the desired barrier heights for both p-type and n-type GeSn while varying the Sn content.First, epitaxially grown GeSn layers with p- and n-type doping are demonstrated. For GeSn doping, the CVD growth of in-situ doped GeSn layers is done using B2H6 for p-type, and AsH3 for n-type. We show high active doping levels in the orders of 1019 and 1020 cm-3 for both p-GeSn and n-GeSn, respectively. These results were obtained from the capacitance voltage measurements (CV) using metal oxide semiconductor (MOS) back-to-back devices. In addition, secondary ion mass spectroscopy (SIMS) and atom probe tomography (APT) data support the high and uniform doping levels.Secondly, since the strong Fermi level pinning (FLP) of Ge is a major problem in the development of n-type contacts due to the loss of metal work function modulation of the barrier height [2], it is expected that the GeSn materials system with low Sn levels exhibits the same behavior, thereby degrading the properties of direct metal/n-GeSn contacts. Therefore, we develop processes aiming to release the Fermi level pinning at metal/GeSn interface, thus restoring the metal work function control of the barrier height. Samples used in this study are CVD grown intrinsic GeSn relaxed samples with increasing Sn concentrations up to 11 at. %. These samples are unintentionally p-type with defect doping levels in the order of 1017 cm-3 as obtained by CV measurements on MOS devices. Our process starts by chemical passivation of these samples, then the deposition and patterning of four metals with different work functions close to the band gap is realized to obtain transfer length method (TLM) structures used for current-voltage (IV) measurements. We then extract the contact properties of these devices and estimate the change of the barrier height induced by the chemical passivation due to the depinning of the FL. This demonstrates the potential use of our process in the fabrication of future metal/n-GeSn contacts. Acknowledgements O.M. acknowledges support from NSERC Canada (Discovery, SPG, and CRD Grants), Canada Research Chairs, Canada Foundation for Innovation, Mitacs, PRIMA Québec, and Defence Canada (Innovation for Defence Excellence and Security, IDEaS).

(Invited) Ultrathin-Body Ge-on-Insulator Mosfet and TFET Technologies

CMOS and tunneling FETs (TFETs) utilizing Ge-On-Insulator (GOI) channels on Si substrates are expected as one of the promising device options for low-power integrated systems. In this paper, we present viable device and process technologies of GOI MOSFETs and TFETs on the Si CMOS platform. High compressive strain, favorable in p-MOSFET applications, is introduced in GOI films by optimizing the Ge condensation process, which is one of the most promising technologies to form ultrathin-body GOI devices. Also, source engineering in GOI layers to realize superior tunnel junctions with steep impurity profiles is developed for TFET applications. The electrical characteristics of GOI MOSFETs and TFETs are presented and analyzed from the viewpoints of applied strain and source junction properties, respectively. One strategy to reduce Vdd is to increase Ion of MOSFETs by employing low effective mass (high velocity) channels. From this viewpoint, Ge/III-V materials are promising. The critical issues for Ge MOSFETs on Si platform are high quality Ge channel formation and application of strain, which are mandatory for overcoming the performance of strained Si/SiGe CMOS. As a technology of the Ge channel formation, we are focusing on the Ge condensation [1]. We previously reported that GOI crystallinity can be enhanced by combining high temperature condensation with intermixing annealing processes [2]. However, no strain was left in the GOI structures because of severe strain relaxation during Ge condensation [1-3], which not only causes defects in the GOI layers but also prevents from enhancing hole mobility in pMOSFETs. Thus, we have proposed and demonstrated a new condensation method with minimized temperature cycles and slow temperature cooling rate [4]. We found that the amount of compressive strain in GOI significantly increases with reducing the cooling rate of GOI after condensation. It was also found that higher compressive strain is obtained by thinning SiGe layers included in starting substrates before condensation [5]. We fabricated 10 nm-thick UTB GOI structure with strain of ~1.7% by using Si/40-nm-thick Si0.75Ge0.25/ SOI starting substrates under the improved condensation recipe. GOI pMOSFETs fabricated on the GOI substrates exhibited the peak hole mobility of as high as 342 cm2/Vs, thanks to high compressive strain. Furthermore, 4.5-nm-thick ETB GOI pMOSFETs with hole mobility enhancement of 3.1 against fully-relaxed GOI ones were achieved without strain relaxation by employing digital thinning with ECR plasma oxidation. Ge is also promising for TFET applications, because of the smaller bandgap and effective mass. Another advantage of Ge is a possibility to realize both n- and p-channel FETs simultaneously, allowing to provide the complementary TFETs in one single material, as similar to Si. However, Ge TFETs previously reported exhibited insufficient characteristics with high Ioff [6, 7]. We recently demonstrated the operation of Ge n- and p-TFETs with the source junctions formed by BF2 implantation and P solid phase diffusion from SOG, respectively [8-10]. It was found that steep source impurity profiles can increase Ion of TFETs [9, 10]. A snowplow effect of NiGe combined with low-energy BF2 + implantation realized an abrupt junction with B profile abruptness less than 5nm/dec and a high doping concentration of around 1021 cm3 by optimizing the Ni thickness. GOI n-TFETs with these source junctions exhibited the Ion/Ioff ratio of 743 and the subthreshold slope of 239 mV/dec at room temperature. It was also found that P diffusion can realize both the high impurity concentration (> 7x1019 cm3) and the steep impurity profile (> 10nm/dec) because of the dopant-concentration-dependent diffusion coefficient. This result indicates that P is a suitable dopant for the source formation of Ge p-TFETs. Using this P diffusion process, Ge p-TFETs with Ion higher than 1.7 μA/μm was obtained at room temperature. However, still high Ioff and S.S. must be much improved by optimizing the source junction formation process and reducing the defect density included in the junctions and the MOS interfaces. This work was supported by JST-CREST Grant Number JPMJCR1332, Japan, and a Grant-in-Aid for Scientific Research (17H06148) from MEXT.

(Invited) Hybrid III-V/Si CMOS Technology Platform: From Materials for Logic to Integrated RF and Photonics

In the past few years, tremendous progress has been achieved in the integration of III-V compound semiconductors on a Si CMOS platform as high-mobility channel materials are foreseen as potential candidates to replace Si channels in advanced CMOS technology nodes. Beyond CMOS scaling, the integration of III-V materials and devices on a Si CMOS platform enables bringing their traditional enhanced functionalities to the chip level: high-speed low-noise RF as well as lasers and sensitive photodetectors. In this presentation, we will review the technologies that we developed to monolithically integrate III-V materials on Si by direct epitaxy in empty oxide cavities or by direct wafer bonding. We will show that record logic n-MOSFET performance can be achieved for ultra-scaled gate lengths (Lg = 13nm), that hybrid III-V/Si(Ge) CMOS functionality can be obtained (inverters, 6T-SRAMs). We will then highlight how 3D monolithic integration enables seamless integration of III-V functionalities on top of Si CMOS front-end for logic as well as for RF and Photonics.

(Invited) Ultrathin-Body Ge-on-Insulator MOSFET and TFET Technologies

CMOS and tunneling FETs (TFETs) utilizing Ge-On-Insulator (GOI) channels on Si substrates are expected as the promising device options for low-power integrated systems. In this paper, we present viable device and process technologies of GOI MOSFETs and TFETs on the Si CMOS platform. High compressive strain, favorable in p-MOSFET applications, is introduced in GOI films by optimizing the Ge condensation process and initial substrate structures, which is one of the most promising technologies to form ultrathin-body GOI p-MOSFETs. Also, source engineering in Ge layers to realize improved tunnel junctions with steep impurity profiles is developed for Ge/GOI TFET applications. In addition, impacts of Ge-based type-II hetero-structures such as Ge/strained-Si and Ge/ZnO on the TFET performance are studied. The electrical characteristics of GOI MOSFETs and TFETs are presented and analyzed from the viewpoints of applied strain, source junction properties and device structures.

(Invited) Ultra-Low Power III-V-Based Mosfets and Tunneling FETs

CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to form these new materials on Si is a common key issue. The wafer bonding technologies are utilized for this purpose. We demonstrate the operation and the electrical characteristics of a variety of III-V MOSFETs and TFETs including the hetero-structures. One strategy to reduce Vdd is to increase Ion of MOSFETs by employing low effective mass (high velocity) channels. From this viewpoint, III-V/Ge materials are promising. One of the most critical problems for III-V MOSFETs on Si platform is high quality III-V channel formation on Si substrates. As a technology of the III-V channel formation, we are focusing on III-V wafer bonding to Si substrates. We have developed a bonding technology extendable to 300-mm Si wafers, where III-V channels are grown on Si with thick buffers and transferred to Si wafers [1]. The high channel quality with a low defect density has been confirmed from the tight leakage current distribution. By using InGaAs-OI substrates fabricated by wafer bonding, we have demonstrated tri-gate In0.3Ga0.7As (3nm)/InAs (3nm)/In0.3Ga0.7As (3nm)-on-insulator quantum well (QW) MOSFETs [2]. High Ion and suppressed short channel effects have been obtained by the narrow width tri-gate structure and the optimized ultrathin quantum-well channels [2, 3]. Also, the other strategy to reduce Vdd is to realize steep slope devices with low sub-threshold swing (S.S.). Here, TFETs are one of the most promising steep slope devices, which have been regarded as mandatory for future scaled LSIs for ultra-low power and IoT applications [4]. There can be two critical issues to realize high performance TFETs. One issue is the choice of the source/channel materials enabling to increase tunneling current. Thus, semiconductors such as Ge and III-V are expected as suitable materials with small and/or direct band gap for enhancing Ion of TFETs. In addition, source/channel junctions composed of type-II hetero-structures are effective in boosting the TFET performance without increase in the junction leakage current. Also, the second critical issue is the defect-less source tunnel junction formation with the optimum source concentration and the steep source impurity profile, which leads to sufficiently thin tunneling width and resulting high tunneling current with minimized leakage currents. From this viewpoint, the technologies to form the source tunnel junctions are of paramount importance. The source regions of n-InGaAs TFETs were formed by selective diffusion from Z-doped SOG [5], which can automatically realize the steep Zn profile, thanks to the concentration-dependent diffusion constant of Zn in InGaAs. We have combined this source with InGaAs quantum well (QW) channels, resulting in enhanced Ion and suppressed Ioff of n-TFETs [6, 7]. The minimum S.S. of 54 mV/dec. has been obtained at room temperature for the In0.53Ga0.47As /In0.67Ga0.33As/In0.53Ga0.47As QW n-TFETs having W/HfO2/Al2O3 gate stacks with CET of 1.4 nm. Type-II hetero-structure GaAsSb/InGaAs TFETs are also regarding as one of the most promising material systems for TFETs. We experimentally observed the operation of vertical n-TFETs with InGaAs channels and GaAsSb sources doped in an in-situ manner during the epitaxial growth, which also realized the steep impurity profiles [8]. While high leakage current in the source junctions degrades the performance at 300 K, TFETs with the high GaAsSb source doping concentration of 1x1020 cm-3 have exhibited the Ion/Ioff ratio of 109, the minimum SS of ~30 mV/dec. and Ion of ~4 mA/mm at 20 K. We have also confirmed the operation of GaAsSb/InGaAs n-TFETs on a Si wafer, which was fabricated by direct wafer bonding [4]. This work was supported by JST-CREST Grant Number JPMJCR1332, Japan, and a Grant-in-Aid for Scientific Research (17H06148) from MEXT. The authors would like to thank Drs. M. Yokoyama, O. Ichikawa, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, Drs. M. Mitsuhara, H. Sugiyama, Hoshi and H. Yokoyama in NTT for their collaborations.

Si Complies with GaN to Overcome Thermal Mismatches for the Heteroepitaxy of Thick GaN on Si.

Heteroepitaxial growth of lattice mismatched materials has advanced through the epitaxy of thin coherently strained layers, the strain sharing in virtual and nanoscale substrates, and the growth of thick films with intermediate strain-relaxed buffer layers. However, the thermal mismatch is not completely resolved in highly mismatched systems such as in GaN-on-Si. Here, geometrical effects and surface faceting to dilate thermal stresses at the surface of selectively grown epitaxial GaN layers on Si are exploited. The growth of thick (19 µm), crack-free, and pure GaN layers on Si with the lowest threading dislocation density of 1.1 × 107 cm-2 achieved to date in GaN-on-Si is demonstrated. With these advances, the first vertical GaN metal-insulator-semiconductor field-effect transistors on Si substrates with low leakage currents and high on/off ratios paving the way for a cost-effective high power device paradigm on an Si CMOS platform are demonstrated.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

III-V/Ge MOS device technologies for low power integrated systems

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Comparison of the AlxGa1–xN/GaN Heterostructures Grown on Silicon-on-Insulator and Bulk-Silicon Substrates

Compared with bulk-Si wafer, Al x Ga1– x N/gallium nitride (GaN) heterostructures grown on a 150-mm silicon-on-insulator (SOI) substrate with a 35-nm-thick Si overlayer are shown to have $\sim 50$ % less wafer bowing. As a result, the 2-D electron gas mobility and the sheet-resistivity uniformity on SOI are improved due to a lower defect density. In terms of device performance, high-electron-mobility transistors (HEMTs) fabricated on the Al x Ga1– x N/GaN-on-SOI exhibit $\sim 20.5$ % higher saturation drain current as compared with the bulk-Si counterparts. However, due to the poorer conductivity of the buried oxide layer, the Al x Ga1– x N/GaN-on-SOI HEMT suffers greater self-heating, with $\sim 50$ K higher channel temperature. With mitigation of self-heating, the Al x Ga1– x N/GaN-on-SOI, in view of its more superior structural and thermal stability, should offer an attractive alternative for integration of the GaN technology with the Si CMOS platform.

Electronic Microarrays in DNA Computing

DNA Computing is a rapidly-developing interdisciplinary area which could benefit from more experimental results to solve practical problems with the current biological tools. In this study, we have integrated microelectronics and molecular biology techniques for the storage of information and basic arithmetic operations via DNA. Using 16 different complementary sequences of DNA, we stored 4 bits of information on an electronic microarray and read the data via the fluorescent signal strength coming from the microarray pads. We also showed the possibility of addition and subtraction of quantities of fluorescently tagged DNA determined via their fluorescent signal strength. We conclude that the hybrid technology we employed, based on a matured Si-CMOS platform, has the potential to strengthen the pursuit of DNA Computation as well as finding its own niche applications.

Electronic Microarrays in DNA Computing

DNA Computing is a rapidly-developing interdisciplinary area which could benefit from more experimental results to solve practical problems with the current biological tools. In this study, we have integrated microelectronics and molecular biology techniques for the storage of information and basic arithmetic operations via DNA. Using 16 different complementary sequences of DNA, we stored 4 bits of information on an electronic microarray and read the data via the fluorescent signal strength coming from the microarray pads. We also showed the possibility of addition and subtraction of quantities of fluorescently tagged DNA determined via their fluorescent signal strength. We conclude that the hybrid technology we employed, based on a matured Si-CMOS platform, has the potential to strengthen the pursuit of DNA computation as well as finding its own niche applications.

DNA as an Engineering Material: From Assembly to Computation on Silicon

ABSTRACTDNA possesses inherent recognition and self-assembly capabilities, making it attractive templates for constructing functional material structures as building blocks for nanoelectronics. Here we report the use of DNA towards the assembly and electronic functionality of nanoarchitectures based on conjugates of carbon nanotubes (CNTs), nanowires (NWs) and DNA computing on Si-CMOS platform. First, assembly of CNTs with DNA is demonstrated and electrical measurements of these nanoarchitectures demonstrate negative differential resistance in the presence of CNT/DNA interfaces, which indicates a biomimetic route to fabricating resonant tunneling diodes. End-to-end assembly of NWs is realized with designed DNA sequences and process is carried on silicon CMOS based microarray platform. Second, this microarray platform is adopted to perform DNA computing. To begin with, the information present in an image is encoded through the concentrations of various DNA strands via selective hybridization and decoded on microarray to recreate the original image. Lately, various satisfiability (SAT) problems, which has long served as a benchmark problem in DNA computing, are solved on this platform via DNA. The goal in a SAT Problem is to determine appropriate assignments of a set of Boolean variables with values of either “true” or “false” such that the output of the whole Boolean formula is true. Other than making 1st time silicon compatible DNA computing, our studies make us understand bio molecules, especially DNA has various advantages for future hybrid technologies.

Multi-technique characterisation of MOVPE-grown GaAs on Si

The heterogeneous integration of III-V materials on a Si CMOS platform offers tremendous prospects for future high-speed and low-power logic applications. That said this integration generates immense scientific and technological challenges. In this work multi-technique characterisation is used to investigate properties of GaAs layers grown by Metal–Organic Vapour Phase Epitaxy (MOVPE) on Si substrates – (100) with 4° offset towards <1 1 0> – under various growth conditions. This being a crucial first step towards the production of III-V template layers with a relatively lower density of defects for selective epitaxial overgrowth of device quality material. The optical and structural properties of heteroepitaxial GaAs are first investigated by micro-Raman spectroscopy and photoluminescence and reflectance measurements. High-resolution X-ray diffraction (HR-XRD) is used to investigate structural properties. Advanced XRD techniques, including double-axis diffraction and X-ray crystallographic mapping are used to evaluate degrees of relaxation and distribution of the grain orientations in the epilayers, respectively. Results obtained from the different methodologies are compared in an attempt to understand growth kinetics of the materials system. The GaAs overlayer grown with annealing at 735 °C following As pre-deposition at 500 °C shows the best crystallinity. Close inspection confirms the growth of epitaxial GaAs preferentially oriented along (100) embedded in a highly textured polycrystalline structure.

Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform

The design and fabrication of a monolithically integrated evanescent-coupled Ge-on-silicon-on-insulator (SOI) photodetector and CMOS circuits were realized on common SOI platform using an ¿electronic-first and photonic-last¿ integration approach. High-performance detector with an integrated Si waveguide was demonstrated on epitaxial Ge-absorbing layer selectively grown on an ultrathin SOI substrate. Performance metrics of photodetector designs featuring vertical and lateral PIN configurations were investigated. When operated at a bias of -1.0 V, a vertical PIN detector achieved a lower <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dark</sub> of ~ 0.57 ¿A as compared to a lateral PIN detector, a value that is below the typical ~ 1 ¿A upper limit acceptable for high-speed-receiver design. Very high responsivity of ~ 0.92 A/W was obtained in both detector designs for a wavelength of 1550 nm, which corresponds to a quantum efficiency of ~ 73%. Impulse response measurements showed that the vertical PIN detector gives rise to a smaller full-width at half-maximum of ~ 24.4 ps over a lateral PIN detector, which corresponds to a -3 dB bandwidth of ~ 11.3 GHz. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> time delay is shown to be the dominant factor limiting the speed performance. Eye patterns (pseudorandom binary sequence 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1) measurement further confirms the achievement of high-speed and low-noise photodetection at a bit rate of 8.5 Gb/s. Excellent transfer and output characteristics have also been achieved by the integrated CMOS inverter circuits in addition to the well-behaved logic functions. The introduction of an additional thermal budget (800 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C) arising from the Ge epitaxy growth has no observable detrimental impact on the short-channel control of the CMOS inverter circuit. In addition, we describe the issues associated with monolithic integration and discuss the potential of Ge-detector/Si CMOS receiver for future optical communication applications.

Defect Reduction of Ge on Si by Selective Epitaxy and Hydrogen Annealing

We demonstrate a promising approach for the monolithic integration of Ge-based nanoelectronics and nanophotonics with Silicon: the selective deposition of Ge on Si by Multiple Hydrogen Annealing for Heteroepitaxy (MHAH). Very high quality Ge layers can be selectively integrated on Si CMOS platform with this technique. We confirm the reduction of dislocation density in Ge layers using AFM surface morphology study. In addition, in situ doping of Ge layers is achieved and MOS capacitor structures are studied.

A New Approach of Electronics and Photonics Convergence on Si CMOS Platform: How to Reduce Device Diversity of Photonics for Integration

Integrated photonics via Si CMOS technology has been a strategic area since electronics and photonics convergence should be the next platform for information technology. The platform is recently referred to as “Si photonics” that attracts much interest of researchers in industries as well as academia in the world. The main goal of Si Photonics is currently to reduce material diversity of photonic devices to pursuing CMOS-compatibility. In contrast, the present paper proposes another route of Si Photonics, reducing diversity of photonic devices. The proposed device unifying functionality of photonics is a microresonator with a pin diode structure that enables the Purcell effect and Franz-Keldysh effect to emit and to modulate light from SiGe alloys.

Hole mobility enhancement of p-MOSFETs using global and local Ge-channel technologies

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on high hole mobility p-MOSFETs using global/local SiGe or Ge channels. There are two directions for introducing SiGe or Ge channels into Si CMOS platform. One is to use SiGe or Ge global substrates and the other is to form SiGe or Ge-channel regions locally on Si wafers. In both cases, the Ge condensation technique, where Ge-channel layers are formed by oxidizing SiGe films on SOI substrates, are effectively utilized. As for the global technologies, ultrathin GOI substrates are prepared and used to fabricate high mobility GOI p-MOSFETs. As for the local technologies, SGOI or GOI channels are formed locally in the active area of p-MOSFETs on SOI wafers. It is shown that the hole mobility enhancement factor of as high as 10 is obtained in locally fabricated p-MOSFETs through the effects of high-Ge content and the compressive strain. Furthermore, the local Ge-channel technologies are combined with global SiGe or Ge substrates for pursuing the optimal and individual design of n-MOSFETs and p-MOSFETs on a single Si wafer. The CMOS device composed of strained-Si n-MOSFETs and SGOI p-MOSFETs is successfully integrated on a same wafer, which is a promising CMOS structure under deep sub 100 nm technology nodes.