(Invited) Ultrathin-Body Ge-on-Insulator MOSFET and TFET Technologies

Abstract

CMOS and tunneling FETs (TFETs) utilizing Ge-On-Insulator (GOI) channels on Si substrates are expected as the promising device options for low-power integrated systems. In this paper, we present viable device and process technologies of GOI MOSFETs and TFETs on the Si CMOS platform. High compressive strain, favorable in p-MOSFET applications, is introduced in GOI films by optimizing the Ge condensation process and initial substrate structures, which is one of the most promising technologies to form ultrathin-body GOI p-MOSFETs. Also, source engineering in Ge layers to realize improved tunnel junctions with steep impurity profiles is developed for Ge/GOI TFET applications. In addition, impacts of Ge-based type-II hetero-structures such as Ge/strained-Si and Ge/ZnO on the TFET performance are studied. The electrical characteristics of GOI MOSFETs and TFETs are presented and analyzed from the viewpoints of applied strain, source junction properties and device structures.