Si Cap Research Articles

Impact of diffusionless anneal using dynamic surface anneal on the electrical properties of a high-k/metal gate stack in metal-oxide-semiconductor devices

The impact of diffusionless anneal using dynamic surface anneal (DSA) on the electrical properties of p-type metal-oxide-semiconductor devices with high-k gate dielectrics and metal gate was investigated by monitoring flatband voltage (VFB) and equivalent oxide thickness (EOT) change. Compared to rapid thermal anneal, DSA induces a positive VFB shift without EOT degradation. This finding is attributed to suppression of positively charged oxygen vacancies [Vo++] generation in high-k dielectrics due to the shorter thermal budget. Processing parameters including high-k dielectrics, TiN metal gate thickness, and Si cap deposition temperature significantly affect thermally induced-oxygen vacancies, leading to different VFB behaviors.

Ordered GeSi nanorings grown on patterned Si (001) substrates

An easy approach to fabricate ordered pattern using nanosphere lithography and reactive iron etching technology was demonstrated. Long-range ordered GeSi nanorings with 430 nm period were grown on patterned Si (001) substrates by molecular beam epitaxy. The size and shape of rings were closely associated with the size of capped GeSi quantum dots and the Si capping processes. Statistical analysis on the lateral size distribution shows that the high growth temperature and the long-term annealing can improve the uniformity of nanorings.PACS code1·PACS code2·moreMathematics Subject Classification (2000) MSC code1·MSC code2·more

Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions

Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350 °C. Ge–Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.

The Improvement of High-$k$/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

The impact of the Si cap/SiGe layer on the Hf-based high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal gate SiGe pMOSFET can be obtained with an appropriate <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (~0.3 V), low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> hysteresis ( <; 5 mV), and better I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> - I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> rolloff, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> stability. By the way, the related interface trap density in the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate stack layer can also be reduced, thus improving the device's NBTI and HCI stressing-induced reliability.

Probing the metal gate high k interactions by backside XPS and C-AFM

ABSTRACTThe metal gate high k interaction is one of the dominant processes influencing the electrical performance (Vt, charge accumulation,..) of advanced gate stacks. These interactions are influenced by the entire thermal budget and the presence of reactive elements (on top/ within the material gate) such that relevant measurements can only be performed after a full processing cycle and on a complete gate stack.In such cases the relevant metal gate high k interface is a buried interface located below the metal gate (+ Si cap) and is not accessible for standard characterization methods like x-ray photoemission spectroscopy (XPS) due the limited escape depth of the photoelectrons. Moreover the presence of a conductive metal gate prevents the application of techniques such as conductive atomic force microscopy (C-AFM), to probe the local distribution of the defects, trapping sites and local degradation upon stressing. XPS in combination with layer removal steps like ion beam sputtering will destroy the bonding information and is thus not applicable. Chemical etching of the metal gate stack prior to the XPS measurements requires an extremely precious control of the etching in order to stop 1-2 nm before the high k metal interface.As an alternative we have developed a backside removal approach, that allows us to investigate using techniques such as XPS and C-AFM, the metal gate high k interface.

Influence of CrSi2 nanocrystals on the electrical properties of Au/Si - p/CrSi2 NCs/Si(111) - n mesa-diodes

Semiconducting CrSi2 nanocrystals (NCs) with high density (4×1010 cm−2) and narrow size distribution were grown by reactive deposition epitaxy (RDE) of 0.6 nm Cr at 550 °C on Si(111)7 × 7 substrate. Based on DRS, AFM and TEM results silicon cap epitaxy growth procedure on silicon with high density of CrSi2 NCs has been proposed. Monolithic Si(111)/ CrSi2 NCs/Si(111) structures with three layers of buried CrSi2 NCs have been successfully grown by repeating of CrSi2 NCs formation and silicon epitaxial growth. Electrical characterization of Schottky junctions formed on the grown structures has shown that the formation of point defects generated during the growth of the Si cap layer strongly depends on the cap growth conditions and on the Cr deposition rate.

Threshold voltage model for quantum-well channelpMOSFET with poly SiGe gate

In this paper, threshold voltage model of quantum-well channel pMOSFET with p+polycrystalline SiGe gate and its cut-in voltage model were established based on solving Poisson equation while considering the impact of free carrier. The effects of relevant parameters (Ge concentration of poly SiGe gate, Ge concentration of quantum-well SiGe channel, thickness of oxide layer, thickness of Si cap layer, doping content of quantum-well SiGe channel, and doping content of substrate) on threshold voltage and cut-in voltage of the parasitic channel was analysed by numerical analysis, and obtained the methods to restrain the opening of parasitic channel. The results of the models are in good agreement wih that of experiment reported as well as of ISE simulation.

Second Harmonic Generation Indicates a Better Si/Ge Interface Quality for Higher Temperature and With $\hbox{N}_{2}$ Rather Than With $\hbox{H}_{2}$ as the Carrier Gas

In order for germanium (Ge) to replace silicon in advanced MOSFET channels, proper passivation of Ge is required. For this purpose, an ultrathin epitaxial Si cap was grown on Ge(001), and we applied second harmonic generation (SHG) in order to probe the Si/Ge interface quality. SHG indicates a better interface quality for a growth temperature of 500°C rather than 450°C. Similarly, a better quality of the interface is observed upon replacing the conventional H2 carrier gas with N2. Additionally, from the SHG signal, we were able to extract both the thickness of the native SiO2 layer (~4 monolayers (MLs)] and the thickness of the strained Si layer (relaxation at ~12 MLs). These results are important for building Ge-based electronic components.

High Transport Si/SiGe Heterostructures for CMOS Transistors with Orientation and Strain Enhanced Mobility

We have demonstrated high mobility MOS transistors on high quality epitaxial SiGe films selectively grown on Si (100) substrates. The hole mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by an optimized Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. Surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS further enhance transistor performances. On a (110) surface, the hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a channel direction with appropriate uniaxial channel strain. We finally address low drive current issue of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (ρc).

Ge-rich islands grown on patterned Si substrates by low-energy plasma-enhanced chemicalvapour deposition

Si1 − xGex islands grown on Si patterned substrates have received considerable attention during thelast decade for potential applications in microelectronics and optoelectronics. In thiswork we propose a new methodology to grow Ge-rich islands using a chemicalvapour deposition technique. Electron-beam lithography is used to pre-pattern Sisubstrates, creating material traps. Epitaxial deposition of thin Ge films by low-energyplasma-enhanced chemical vapour deposition then leads to the formation of Ge-richSi1 − xGex islands(x > 0.8) with a homogeneous size distribution, precisely positioned with respect tothe substrate pattern. The island morphology was characterized by atomicforce microscopy, and the Ge content and strain in the islands was studied byμRaman spectroscopy. This characterization indicates a uniform distribution of islands with high Gecontent and low strain: this suggests that the relatively high growth rate (0.1 nm s − 1) and lowtemperature (650 °C) used is able to limit Si intermixing, while maintaining a long enough adatom diffusionlength to prevent nucleation of islands outside pits. This offers the novel possibility of usingthese Ge-rich islands to induce strain in a Si cap.

Formation of Nanopits in Si Capping Layers on SiGe Quantum Dots.

In-situ annealing at a high temperature of 640°C was performed for a low temperature grown Si capping layer, which was grown at 300°C on SiGe self-assembled quantum dots with a thickness of 50 nm. Square nanopits, with a depth of about 8 nm and boundaries along 〈110〉, are formed in the Si capping layer after annealing. Cross-sectional transmission electron microscopy observation shows that each nanopit is located right over one dot with one to one correspondence. The detailed migration of Si atoms for the nanopit formation is revealed by in-situ annealing at a low temperature of 540°C. The final well-defined profiles of the nanopits indicate that both strain energy and surface energy play roles during the nanopit formation, and the nanopits are stable at 640°C. A subsequent growth of Ge on the nanopit-patterned surface results in the formation of SiGe quantum dot molecules around the nanopits.

The Effect of a Si Capping Layer on RF Characteristics of High-$k$/Metal Gate SiGe Channel pMOSFETs

We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.

Lifting, welding, and packaging of a quality-factor-controllable micromachined inductor using magnetic fields

This study demonstrates a novel approach to lift the inductor from the lossy substrate by static magnetic field. The lift angle of the inductor, which tuned by a position stage, is employed to control the quality factor of the inductor. The lifted inductor is then welded by localized induction heating using the ac magnetic field. Thus, the heating-induced thermal problem is prevented. In addition, the inductor is also simultaneously packaged inside a Si capping by the alternating magnetic field. To demonstrate the feasibility of the proposed concept, the meander strip inductor was fabricated and tested. The radio frequency performance of the inductor at various tilting angles away from the substrate (0, 45, and 90 deg) was characterized by using a two-port vector network analyzer. The quality factor has been improved from 4.2 (at the central frequency of 0.64 GHz) to 7.9 (at the central frequency of 0.74 GHz), as the lift angle increased from 0 to 90 deg. In other words, the central frequency of the inductor can also be varied from 0.64 to 0.74 GHz. Measurement results also indicate that the bonded Si capping has a good shear strength of 23.5 MPa.

Study of HfO2/Si/Strained-Ge/SiGe Using Angle Resolved X-ray Photoelectron Spectroscopy

We have investigated the influence of Si-cap layer and the post deposition annealing (PDA) on compositional depth profiles and chemical structures of HfO2/Si-cap/strained Ge/SiGe/Si interfaces by angle-resolved X-ray photoemission spectroscopy. Analyses of Ge 2p, Si 1s and O 1s spectra show that strained-Ge layer was oxidized during the deposition of HfO2 in the case of 1 nm in thickness of the Si cap layer and that Ge layer was not oxidized in the case of 3nm and 5nm in thickness of the Si cap layer.

Phosphorus Atomic Layer Doping in Si Using PH3

Atomic layer doping of P (P-ALD) in Si is investigated using reduced pressure chemical vapor deposition (RPCVD). For P-ALD, PH3 exposure on Si (100) surface followed by Si cap layer deposition using SiH4 or Si2H6 is performed. P adsorption is suppressed by hydrogen-termination of the Si surface. On the hydrogen-free Si surface, the P adsorption is increasing with increasing PH3 exposure temperature saturating at temperatures above 600oC. P adsorption is also increasing with increasing PH3 exposure time. It tends to saturate at long exposure time indicating a self-limitation of the process. By Si deposition using Si2H6, higher P peak concentration and higher P doping level in the Si cap layer is observed compared to those with SiH4 based Si deposition. For both SiH4 and Si2H6 based capping process lower P segregation is observed by lowering the growth temperature.

Effects of Halo Doping and Si Capping Layer Thickness on Total-Dose Effects in Ge p-MOSFETs

The total-dose response of Ge p-MOSFETs and p+-n junction diodes is reported for devices fabricated with several process variations. Radiation-induced reduction of the on-off current ratio increases with halo-doping density. Increasing the number of Si monolayers at the substrate/dielectric interface reduces total-dose sensitivity for p-MOSFETs. Reduced mobility degradation is observed after irradiation for devices with a higher number of Si monolayers. The radiation-induced increase in junction leakage is related to the increasing perimeter component of the leakage current. MOSFETs with a higher number of Si monolayers at the dielectric/substrate interface also have reduced perimeter leakage current. Diode leakage current increases with increasing halo-doping density.

Retrograde Melting and Internal Liquid Gettering in Silicon

Retrograde Melting and Internal Liquid Gettering in Silicon

Strain engineering in Si via closely stacked, site-controlled SiGe islands

The authors report on the fabrication and detailed structural characterization of ordered arrays of vertically stacked SiGe/Si(001) island pairs. By a proper choice of growth parameters, islands which have both large sizes and high Ge fraction are obtained in the upper layer. Finite element method calculations of the strain distribution reveal that (i) the Si spacer between a pair of islands can act as a lateral quantum dot molecule made of four nearby dots for electrons and (ii) the tensile strain in a Si cap deposited on top of the stack is significantly enhanced with respect to a single layer.

(Invited) Electrical Characterization of Ge-pFETs with HfO2/TiN Metal Gate: Review of Possible Defects Impacting the Hole Mobility

Recently, best 65 nm Ge pMOSFET performance has been reported with a standard Si CMOS HfO2 gate stack module (1). In this contribution, we investigated in more detail how device performance, especially the hole mobility, depends on the characteristics of layers featuring the gate dielectric (HfO2, SiO2 and the Si cap layer). We found that many point defects are involved in the mobility control. We specifically highlight the role of defects linked to the Si cap integration. A critical Si thickness is also extracted, separating two important regimes. We finally report the difference in hole-mobility-limiting mechanisms between Ge devices integrating two different Epi-Si passivation schemes. Based on low temperature measurements, the promising Si3H8 process shows an additional coulomb scattering mechanism compared to SiH4.

Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics

Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high-k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si1 - x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology. Device simulations are used to explain the experimental threshold voltage trends with varying Si1 - x Gex thicknesses, boron counterdopings, and gate work functions.