Si Bipolar Technology Research Articles

Cryogenic low-noise amplifiers for measurements with superconducting detectors.

We designed, implemented, and characterized differential amplifiers for cryogenic temperatures based on Si bipolar junction transistor technology. The amplifiers show high gain values of more than 60 dB at 300, 77, and 48 K. The minimum voltage noise spectral density was achieved at 77 K and corresponded to 0.33 nV/Hz0.5 with a flicker noise of 20 Hz. The maximum voltage gain was 70 dB at 77 K for a frequency range from DC to 17 kHz. We experimentally show that the parallel differential circuit design allows for a reduction of the voltage noise from 0.55 to 0.33 nV/Hz0.5 at 77 K.

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the limited pull-in range, and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.

A bootstrap technique for wideband amplifiers

We propose a novel topology for a wideband amplifier, that exploits a series-shunt positive capacitive feedback to compensate the "pole-splitting" action of base-collector capacitance C/sub /spl mu//. Feedback is applied to a buffered differential pair to obtain a bootstrap action; the compensation network requires two capacitors and emitter degeneration resistors in the differential pair, and does not affect biasing and low frequency behavior of the amplifier. We present an AC model of the amplifier to get an insight in the behavior of the proposed compensation technique and to obtain design guidelines for maximizing the gain-bandwidth product. A case study using a 27 GHz-f/sub T/ Si bipolar technology has shown a 160% gain-bandwidth enhancement with respect to a simple differential pair, and a 27% enhancement with respect to other topologies proposed in the literature.

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter /spl zeta//spl omega//sub n/ (/spl zeta/ is a damping factor and /spl omega//sub n/ is the natural angular frequency of the PLL), and that the optimization focusing on the /spl omega//sub n/ dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-/spl mu/m Si bipolar technology (f/sub T/ = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers).

A high-IP3 RF receiver chip set for mobile radio base stations up to 2 GHz

We present a monolithically integrated high third-order intercept point (IP3) radio frequency (RF) receiver chip set for mobile radio base stations up to 2 GHz, in a 25-GHz f/sub T/ Si bipolar production technology. The chip set consists of a RF preamplifier, active mixer circuits, and an intermediate frequency (IF) limiter. The preamplifier gain is 12 dB, the noise figure is 5.5 dB at 900 MHz, and the output (OIP3) is up to +24 dBm depending on supply voltage. The two different mixers provide a conversion gain of 1.5 dB up to 3 dB, an OIP3 in the range of +21 dBm up to +29 dBm, and a minimal single sideband (SSB) noise figure of 13 dB. The IF limiter shows an excellent limiting characteristic at 10 dBm output power and has a high bandwidth of more than 1 GHz.

5 V, 10 Gbit/s optical receiver module using Si-bipolarIC

A 10 Gbit/s optical receiver module using a Si-bipolar IC has been developed. For low power and low cost, a pure Si-bipolar IC is used in place of a GaAs IC, which is commonly used for over 10 Gbit/s. To widen the frequency bandwidth, multifeedback techniques and a two-stage buffer configuration are used in the preamplifier IC. In addition, a differential circuit configuration is used for stable operation at high frequency. The IC was fabricated using 0.25 µm Si-bipolar technology. The module exhibits sensitivity of < –16 dBm for 10 Gbit/s data with an input dynamic range > 15 dB. Small power consumption of 410 mW is achieved with the single power-supply voltage of +5 V.

Investigation on low-voltage low-power silicon bipolar design topology for high-speed digital circuits

This paper investigates a bipolar design topology which is suitable to operate from a voltage supply well below 1.5 V, while maintaining the ability of high frequency operation. The topology has been applied in the design of different divide-by-4 circuits, utilizing a 20-GHz 0.6-/spl mu/m Si bipolar technology. The different versions featured slight modifications in the architecture of the logic cells and the influence on the frequency and supply voltage range of operation has been investigated. Measurements have shown operation from 1.0-V supply voltage and up to 4.2-GHz input frequency to 1.5 V and up to 6 GHz. The power consumption is approximately 0.3 mW/latch and 1.2 mW/latch, respectively.

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LAN's and WAN's. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs.

2.5 Gbit/s clock and data recovery circuit IC usingnovel duplicated PLL technique

A 2.5 Gbit/s monolithic clock and data recovery integrated circuit (CDR IC) based on a novel duplicated phase-locked loop (PLL) technique has been fabricated using 0.5 /spl mu/m Si bipolar technology. This CDR IC operates more stably in that it can tolerate greater variations in temperature and supply voltage while continuing to meet the specifications for jitter characteristics stipulated in the ITU-T recommendations.

An ultracompact, 2-cc-size, low-power 2.5-Gb/s optical receiver module incorporating an MU receptacle

This paper describes an ultracompact, -3-V-supply, 2.5-Gb/s optical receiver module. For miniaturization of a gigabit-class receiver module, we used multichip configuration and bump technology, and we incorporated a miniature unit-coupling (MU) receptacle for small-size optical interface. To eliminate required external adjustment devices in the module for reduction of module size and assembling cost, we introduced new circuit techniques; the multistage automatic offset canceling technique is used for the postamplifier, and the sample-and-hold phase-locked loop (PLL) technique is employed for the clock and data recovery circuits. All the ICs were designed to operate at a low DC power supply of -3 V. The IC current was reduced by using 0.5-/spl mu/m Si bipolar process technology. The volume is only 2 cc (9/spl times/30.3/spl times/ 7.7 mm/sup 3/), including the MU receptacle. The experimental results show that the receiver has a wide dynamic range, from more than -2 to -19.4 dBm in optical input. These results were obtained without making any external adjustments. The module consumes a total power of 0.64 W.

A 5-GHz frequency-doubling quadrature modulator with a ring-type local oscillator

The direct-conversion quadrature modulator described here was developed by using a frequency-doubling circuit technique so that the modulator and the local oscillator can be integrated on a single silicon chip. The local oscillation frequency in the modulator can be reduced to half the carrier frequency, and this enables the integration on a single chip. A three-level mixer with a newly designed symmetrical topology for two local oscillator inputs is used for the frequency doubling, so the image component levels of the modulated signals are low. When the modulator was implemented on a single chip by using Si-bipolar process technology with a cutoff frequency of 40 GHz, the image ratio at a carrier frequency of 5 GHz was less than -34 dBc.

LOW TRANSIMPEDANCE-FLUCTUATION DESIGN FOR 10-GHz Si-BIPOLAR PREAMPLIFIER IN 10-Gb/s OPTICAL TRANSMISSION SYSTEMS

Design considerations concerning Si preamplifiers for 10-Gb/s optical transmission systems are discussed. A preamplifier with 300-Ω transimpedance was designed by focusing on attaining low transimpedance fluctuation in the frequency response despite bias variation caused by the photo current. To ensure good design accuracy, we optimized the current density of the transistor and the open-loop voltage gain using measured results to obtain the desired bandwidth. We also developed a low-loss pad structure that has U-grooves to improve the bandwidth. The U-grooves increase the pad parasitic resistance and reduce signal-loss from pad to Si substrate. A preamplifier IC fabricated using a Si bipolar technology with fT of 35-GHz provided a bandwidth of 10.2 GHz, transimpedance fluctuation within 0.5 dB, an input dynamic range of up to 1.6 mA p-p, and a low averaged input noise current density of 11.5 [Formula: see text].

RFIC's for mobile communication systems using SiGe bipolar technology

We report on design aspects and the implementation of RF integrated circuits (RFIC's) using TEMIC's SiGe heterojunction bipolar transistor (HBT) technology. SiGe HBT's with 50-GHz f/sub T/ and f/sub max/ were obtained by a production process including polysilicon resistors, nitride capacitors, and spiral inductors showing Q values up to 10. RF noise figures down to 1 dB at 2 GHz with an associated gain of 14-dB and 1-kHz 1/f corner frequency were obtained. The differences between the device parameters of Si bipolar junction transistor (BJT) and SiGe HBT technology and their influence on IC design are discussed. Design and measurement results of RFIC's, including a low-noise amplifier (LNA) and a power amplifier (PA) for application in a 1.9-GHz digital enhanced cordless telecommunications (DECT) RF front-end and 900-MHz preamplifier for a global system for mobile communication (GSM) power module are presented.

Modeling and measurement of substrate coupling in Si-bipolar IC's up to 40 GHz

Parasitic substrate coupling can severely degrade the performance of high-speed ICs and must be considered carefully in circuit design. Therefore, this paper proposes several equivalent circuits that are well suited for modeling substrate coupling up to very high frequencies with standard circuit simulators such as SPICE. Their element values can be calculated for arbitrary layout configurations from numerical simulations (using our SUbstrate SImulator SUSI), which are based on experimentally determined, specific technological/electrical data. The validity of both the simulator and the equivalent circuits has been verified by on-wafer measurements up to 40 GHz, the highest frequency reported so far for modeling of substrate coupling. For this, special test structures were designed and fabricated in an advanced Si-bipolar technology. This work is focused on substrate modeling in very-high-speed rather than in complex ICs.

Jitter-suppressed low-power 2.5 Gbit/s clock anddata recovery IC without high-Q components

A 2.5 bit/s monolithic clock and data recovery (CDR) IC using a PLL technique is fabricated using Si bipolar technology. The CDR IC provides suppressed jitter characteristics with a low power consumption. To our knowledge, this is the first report of a single-chip 2.5 Gbit/s CDR IC, the jitter characteristics of which meet all three types of STM-16 jitter specifications described in ITU-T recommendations.

Self-aligned metal/IDP Si bipolar technology with 12-ps ECL and 45-GHz dynamic frequency divider

Ultra-high-speed operation using a self-aligned stacked metal/in situ doped poly-Si (IDP) (referred to as SMI) Si bipolar transistor technology that offers low base resistance while keeping collector capacitance low is demonstrated. This SMI technology provides a base electrode consisting of metal and in situ boron-doped poly-Si (IBDP). Here, metal is fully stacked on the IBDP by using selective tungsten CVD in the self-aligned manner, which means that the structure has low sheet resistance and the fabrication process has a small thermal budget. Thus, low base resistance and low collector capacitance can be achieved. Three types of base electrode, an IBDP, a partially stacked SMI, and a fully stacked SMI, were fabricated to investigate the usefulness of this SMI technology and the importance of the low base resistance. Using the SMI technology, the base resistance was reduced to about 40% and the maximum oscillation frequency was raised by about 30% with respect to the conventional poly-Si base electrode. This technology makes it possible to obtain ultra-high-speed operation with a 12-ps gate-delay emitter-coupled logic (ECL) circuit, and with 45-GHz-dynamic and 28-GHz-static frequency dividers, even when using a conventional ion-implanted base.

10 Gbit/s decision and 1:16 demultiplexing circuitin Si production technology

An integrated circuit consisting of a decision circuit/1:16 demultiplexer was realised for use in 10 Gbit/s SDH/SONET transmission systems. The circuit implements the necessary high speed functions phase detector and decision threshold control as well. It was designed using a state-of-the-art Si bipolar technology with the aim to be used in transmission system products.

A Si 1.8 GHz RLC filter with tunable center frequency and quality factor

A second-order active bandpass filter using integrated inductors was implemented in Si bipolar technology. The filter uses special techniques to make the quality factor and the center frequency tunable. For a nominal center frequency of 1.8 GHz and a quality factor of 35, the filter has 1 dB compression dynamic range of 40 dB, and draws 8.7 mA from a 2.8 V supply.

A 1.28-GHz sigma-delta modulator for video A/D-conversion

This paper describes the implementation and potential applications of a sigma-delta A/D-converter. A second-order low-pass approach with a single-bit quantization is used. Test ICs using a 20 GHz f/sub T/ Si bipolar technology were fabricated and proven functional.

A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator

A 2-GHz Si-bipolar direct-conversion quadrature modulator with a wide bandwidth is described. It operates at a low supply-voltage of 2 V and features a "current-folded" double-balanced mixer with a two-stacked-transistor configuration, and a tunable RC/CR 90/spl deg/ phase shifter that reduces the amplitude imbalance and the phase error over a wide bandwidth (0.8 to 2 GHz). The modulator is implemented using 18-GHz Si-bipolar technology and dissipates only 68 mW at 2 V. The image ratio at 2 GHz is about -37 dBc, corresponding to a phase error of 1.6/spl deg/. Moreover, both second-order and third-order products, and local signal leakage are less than -40 dBc.