Si Bipolar Technology Research Articles

50 Gbit/s time-division multiplexer in Si-bipolartechnology

A 2:1 time-division multiplexer is presented which operates up to 50 Gbit/s. This is the highest data rate ever achieved by an integrated circuit in any technology. The output voltage swing is 1 V peak-to-peak at 40 Gbit/s and 0.6 V peak-to-peak at 50 Gbit/s (at 50 /spl Omega/ on-chip matching). The chips were fabricated in an advanced Si-bipolar technology (f/sub T/=35 GHz) and mounted on a comparatively simple measuring socket.

Low-noise, high-transimpedance Si-bipolar AGC amplifier for 10 Gb/s optical-fiber links

A two chip low-noise transimpedance amplifier with automatic gain control (AGC) is presented. The amplifier has been developed for a 10-Gb/s optical-fiber system and fabricated in a Si-bipolar production technology. The maximum transimpedance is as high as 45 k/spl Omega/ and the electrical input dynamic range is 33 dB. >

Over 20 Gbit/s throughput ATM crosspoint switchlarge scale integrated circuit using Si bipolar technology

An ATM crosspoint switch large scale integrated circuit (LSI) for a high-speed high-capacity input and output buffering ATM switching system was developed through the use of Si bipolar technology. It was confirmed that the LSI could attain 28.8 Gbit/s throughput in 32-parallel-signal operation at 900 Mbit/s. This throughput is ~40% higher than the highest level ever previously reported.

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-/spl mu/m photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV/sub p-p/. An extremely high input sensitivity of 15 mV/sub p-p/ and a wide phase margin of 260/spl deg/ at 10 Gb/s are achieved. >

A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits

A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-/spl mu/m advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively. >

A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2/sup 23/-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Deep submicrometer super self-aligned Si bipolar technology with 25.4 ps ECL

A new deep submicron double-poly self-aligned Si bipolar technology has been developed using a 0.3-/spl mu/m design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. This technology is called "High-Performance Super Self-Aligned Process Technology" or HSST. 0.3-/spl mu/m minimum patterning is achieved by electron-beam direct writing technology. The HSST bipolar transistor is 2.5 times smaller than the previous 1-/spl mu/m SST-1B. Owing to its horizontal reduction and an f/sub T/ of 22.3 GHz at V/sub ce/=1 V, the ECL gate attains 25.4 ps/G at 1.58 mA, which is a 30% improvement on the SST-1B. By including parasitic capacitances of the base polyelectrode and polyresistors, the ECL delay time is accurately simulated for low-power operation. It is shown that the HSST is a very promising technology for the development of future high-speed communication systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Static frequency dividers for high operating speed (25 GHz, 170 mW) and low power consumption (16 GHz, 8 mW) in selective epitaxial Si bipolar technology

Static frequency dividers have been fabricated in a selective epitaxial bipolar technology using 0.8 mu m lithography. The measured maximum frequency of 25 GHz is the highest value reported for static silicon dividers. Moreover, a 16 GHz low-power version is presented which consumes only 8 mW in the first stage.

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 μm lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.

A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBTs, MESFETs, and Si BJTs. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2 Gb/s 1:8 demultiplexer are described. These multigigabit LSIs have been achieved mainly by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (f/sub max/), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSIs are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding. >

Active compensation of interconnection losses for multi-GHz clock distribution networks

The authors propose an active compensation scheme for losses in heavily loaded high-speed differential clock distribution networks using Si bipolar integrated circuit technology. The compensation network consists of negative impedance converter circuitry and provides performance improvements up to multi-gigahertz frequencies. Even though the compensation technique is proposed in the context of Si bipolar multilevel current switch logic circuits, the analogous application with other high-speed technologies is possible where loading dominates the on-chip transmission line characteristics. The authors give general design guidelines and reports simulation results for a 2-GHz clock distribution example problem using parameters of state-of-the-art single-poly self-aligned Si bipolar transistors. >

An experimental 5-Gb/s 16*16 Si-bipolar crosspoint switch

An experimental 16*16, nonblocking, asynchronous crosspoint switch with a data rate of 5-Gb/s per channel is presented. Implemented in a 0.8- mu m, double-poly, self-aligned Si-bipolar ECL technology, the 3-mm*3-mm chip, featuring a multiplexer-type architecture with a three-device crosspoint cell, demonstrates a nominal data path delay of 420 ps with 12.5-ps RMS jitter and a setup time of 1 ns and dissipates about 4.6 W. >

High-speed analogue neural-network LSI employing super-selfaligned Si bipolar process technology

A high-speed analogue neural-network LSI is developed using super selfaligned Si bipolar process technology. The LSI contains four neurons and 16 electrically-modifiable synaptic weights. Neural processing is demonstrated with ‘exclusive OR’ logic at a speed of 150 megapatterns per second.

A Si-bipolar technology for optical fiber transmission rates above 10 Gb/s

A multiplexer operating at up to 12 Gb/s has been demonstrated using a simple, but optimized, silicon bipolar technology with 2 mu m lithography. Using this simple but optimized technology, a 12 Gb/s multiplexer was implemented. Circuit simulations predict the increase of the bit rate up to at least 15 Gb/s by changing to the 1.5 mu m lithography. The results of experimental investigations and circuit simulations show that low-cost silicon-based bipolar circuits will be available for future optical-fiber transmission systems with data rates higher than 10 Gb/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate

An 8-b flash analog-digital (A/D) converter (ADC) LSI for high-speed data acquisition systems such as digital oscilloscopes and wave digitizers is described. This converter can convert analog input signals over the Nyquist frequency (up to 200 MHz) at a conversion rate of 300 megasamples per second (Ms/s) without glitch errors. In addition, it can be operated at up to 440 Ms/s when input frequency is as low as 100 kHz. This ADC is fabricated by a 2.5- mu m, 10-GHz f/sub T/, Si bipolar technology called the advanced sidewall base contact structure (advanced SICOS) technology. For high-performance glitch error suppression, an inhibitory circuit and a comparator design with an inner clock buffer are developed. Both techniques require few hardware additions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Proposal for a versatile monolithic multi-Gbit/s m-sequence test system

A multi-functional system is proposed which combines four important features for m-sequence applications: Generation of m-sequences, detection of bit errors, derivation of word synchronisation pulses, and scrambling as well as descrambling of a data stream. Circuit simulations show that a monolithic realisation for data rates of more than 10Gbit/s is feasible using a simple self-aligning Si bipolar technology.

11.4 Gbit/s multiplexer IC employing submicron Si bipolar technology for use in future broadband telecommunications systems

This letter presents an 11.4 Gbit/s, 2:1 multiplexer using a 0.6 μm wide, nonpolysilicon emitter Si bipolar technology. The chip measures 0.9 × 0.8 mm2, dissipates 350 mW with a 5V supply and operates at the fastest data rate reported for a multiplexer in any IC technology.

3.5 GHz bandwidth, 30 dB gain Si monolithic amplifier

A new high-gain, wideband Si monolithic amplifier utilising a new parallel feedback and adjustable peaking technique has been developed using a high-speed Si bipolar process technology. An objective of the design was to enhance gain and bandwidth performance by preventing parasitic oscillation. This IC achieves a wide bandwidth of DC-3.5 GHz, and a high gain of 30 dB. Furthermore, a noise level of 5 dB at 1 GHz and a total power dissipation of 180 mW at a power supply voltage of 6 V were attained.

Si bipolar 2-GHz 6-bit flash A/D conversion LSI

A gigahertz-sampling-rate flash A/D (analog/digital)-conversion LSI using high-speed Si bipolar technology (SST-1B) is investigated. To improve comparator speed, a circuit technology to minimize the comparator-speed limiting factors with minimum power is investigated and applied. To enhance the dynamic accuracy, speed mismatch among comparators is also minimized using this circuit technology. To improve encoder speed, a quasi-Gray code is adopted and glitch noise is reduced with this code. The LSI performance at 1-GHz sampling rate is measured with a gigahertz-operation data acquisition system developed with the SST MSI family, and effective bits of 5.8 at an input frequency of 100 MHz and 4.8 at 500 MHz are achieved. This LSI also demonstrates the feasibility of a single-chip flash A/D converter with a gigahertz sampling rate using Si bipolar technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Static 7 GHz frequency divider IC based on a 2 μm Si bipolar technology

A static 8:1 frequency divider IC operating at up to 7 GHz has been realised using a preproduction silicon bipolar technology with 2 μm lithography. This technology is characterised by a self-aligned double polysilicon emitter-base structure and oxide wall isolation. The high upper frequency limit, not yet achieved with comparable 2 μm technologies, was attained by careful circuit design and optimisation.