Short-length Low-density Parity-check Codes Research Articles

High performance binary LDPC-coded OFDM systems over indoor PLC channels

Power line communication (PLC) technology is actually among the most renowned technologies for home environments due to their low-cost installation opportunities. In this study, the bit error rate (BER) performances of binary low-density parity check (LDPC) coded orthogonal frequency-division multiplexing (OFDM) systems have been considered over indoor PLC channels. Performances comparison of diverse soft and hard decision LDPC decoder schemes such as Min-Sum (MS), weighted bit flipping (WBF), gradient descent bit-flip (GDBF), noisy gradient descent bit-flip (NGDBF) and its few variants including the single-bit NGDBF (S-NGDBF), multi-bit NGDBF (M-NGDBF) and smoothed-multi-bit NGDBF (SM-NGDBF) decoders were examined in the modeled network. To evaluate the BER performance analyses three different PLC channel scenarios were generated by using new and more realistic PLC channel model proposal were also employed. All of the simulations performed in Canete’s PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the MS or SM-NGDBF decoding algorithms are employed on the receiver side.

A comparative simulation study of different decoding schemes in LDPC coded OFDM systems for NB-PLC channel

In this paper, we study the performance of Low density Parity Check (LDPC) coded orthogonal frequency-division multiplexing (COFDM) systems when they are applied on the short data block of a narrowband (NB) power line communications (PLC) channel. In the modelled system simulations have been performed using different code lengths. It is assumed that the channel has a multipath propagation with two different noise scenarios: AWGN background noise with and without the presence of impulsive noise. Performances of Various soft and hard decision LDPC decoder schemes such as belief propagation (BP), weighted bit flipping (WBF), improved weighted bit flipping (IWBF) and implementation-efficient reliability ratio based weighted bit flipping (IRRWBF) decoders were investigated. It has been shown for all simulations performed in PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the BP decoding algorithms are employed on the receiver side.

Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10 2 (10 4 ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

On Efficient Design of LDPC Decoders for Wireless Sensor Networks

Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation in digital communication systems. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However,traditional hardware implementation of LDPC decoders require large amount of resources, rendering them unsuitable for use in energy constrained sensor nodes of wireless sensor networks (WSN). This paper investigates the use of short-length LDPC codes for error correction in WSN. It presents the LDPC decoder designs, implementation, resource requirement and power consumption to judge their suitability for use in the sensor nodes of WSN. Due to the complex interconnections among the variable and check nodes of LDPC decoders, it is very time consuming to use traditional hardware description language (HDL) based approach to design these decoders. This paper presents an efficient automated high-level approach to designing LDPC decoders using a collection of high-level modelingtools. The automated high-level design methodology provides a complete design flow to quickly and automatically generate, test and investigate the optimum (length) LDPC codes for wireless sensor networks to satisfy the energy constraints while providing acceptable bit-error-rate performance.

Highly reliable LDPC coded data transfer in home networks by using Canete’s PLC channel model

Power line communication (PLC) methods are presently among the most popular technologies for home environments due to their low-cost installation opportunities. In this study, the bit error rate (BER) performance of low-density parity-check (LDPC) coded communication systems is presented by using Canete’s PLC channel model over power lines in home networks. Various soft and hard decision LDPC decoders such as belief propagation (BP), weighted bit flipping (WBF), improved weighted bit flipping (IWBF) and implementation-efficient reliability ratio based weighted bit flipping (IRRWBF) decoders are employed in the modeled network. All of the simulations performed in Canete’s PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the BP or IRRWBF decoding algorithms are employed on the receiver side.

Check Node Reliability-Based Scheduling for BP Decoding of Non-Binary LDPC Codes

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

Weighted-Bit-Flipping-Based Sequential Scheduling Decoding Algorithms for LDPC Codes

Low-density parity-check (LDPC) codes can be applied in a lot of different scenarios such as video broadcasting and satellite communications. LDPC codes are commonly decoded by an iterative algorithm called belief propagation (BP) over the corresponding Tanner graph. The original BP updates all the variable-nodes simultaneously, followed by all the check-nodes simultaneously as well. We propose a sequential scheduling algorithm based on weighted bit-flipping (WBF) algorithm for the sake of improving the convergence speed. Notoriously, WBF is a low-complexity and simple algorithm. We combine it with BP to obtain advantages of these two algorithms. Flipping function used in WBF is borrowed to determine the priority of scheduling. Simulation results show that it can provide a good tradeoff between FER performance and computation complexity for short-length LDPC codes.

Blind reconciliation

Information reconciliation is a crucial procedure in the classical post-processing of quantum key distribution (QKD). Poor reconciliation efficiency, revealing more information than strictly needed, may compromise the maximum attainable distance, while poor performance of the algorithm limits the practical throughput in a QKD device. Historically, reconciliation has been mainly done using close to minimal information disclosure but heavily interactive procedures, like \textit{Cascade}, or using less efficient but also less interactive ---just one message is exchanged--- procedures, like the ones based in low-density parity-check (LDPC) codes. The price to pay in the LDPC case is that good efficiency is only attained for very long codes and in a very narrow range centered around the quantum bit error rate (QBER) that the code was designed to reconcile, thus forcing to have several codes if a broad range of QBER needs to be catered for. Real world implementations of these methods are thus very demanding, either on computational or communication resources or both, to the extent that the last generation of GHz clocked QKD systems are finding a bottleneck in the classical part. In order to produce compact, high performance and reliable QKD systems it would be highly desirable to remove these problems. Here we analyse the use of short-length LDPC codes in the information reconciliation context using a low interactivity, \textit{blind}, protocol that avoids an a priori error rate estimation. We demonstrate that $2 \times 10^3$ bits length LDPC codes are suitable for blind reconciliation. Such codes are of high interest in practice, since they can be used for hardware implementations with very high throughput.

Constructing Short-Length Irregular LDPC Codes with Low Error Floor

Trapping sets (TSs) are known to cause error floors in regular and irregular low-density parity-check (LDPC) codes. By avoiding major error-contributing TSs during the code construction process, codes with low error floors can effectively be built. In it has been shown that TSs labeled as [w;u] are considered as being equivalent under the automorphism of the graph and are therefore contributing equally to the error floor. However, TSs with the same label [w;u] are not identical in general, particularly for the case of irregular LDPC codes. In this paper, we introduce a parameter e that can identify the number of "distinguishable" cycles in the connected subgraph induced by an elementary trapping set. Further, we propose a code construction algorithm, namely the Progressive-Edge-Growth Approximate-minimum-Cycle-Set-Extrinsic-message-degree (PEG-ACSE) method, that aims to avoid small elementary trapping sets (ETSs), particularly detrimental ETSs. We also develop theorems evaluating the minimum possible ETSs formed by PEG construction algorithms in general. We compare the characteristics of the codes built using the proposed method and those built using PEG-only or PEG-Approximate-minimum-Cycle-Extrinsic-message-degree (PEG-ACE) methods. Results from simulations show that the codes constructed using the proposed PEG-ACSE method produce lower error rates, particularly at the high signal-to-noise (SNR) region, compared with codes constructed using other PEG-based algorithms.

Lowering the Error Floor of Optimized Short-Block-Length LDPC-Coded OFDM via Spreading

In this paper, short-block-length low-density parity-check (LDPC) codes are optimized and introduced, along with Walsh-Hadamard spreading, to orthogonal frequency-division multiplexing (OFDM) systems. Prior research has shown that lowering the threshold associated with LDPC codes results in higher error floors. The error floor becomes more pronounced for short-block-length LDPC codes that have been proposed for many wireless standards. In this paper, we show that the use of spreading along with code optimization and girth conditioning not only improves the performance but also lowers the error floor for short-length LDPC codes. Density evolution and differential evolution methods are used during the optimization phase of the codes for the frequency-uncorrelated Rayleigh fading channel. Performance results are obtained for extended irregular repeat-accumulate codes and progressive edge-growth algorithm generated codes. Next, the performances of LDPC-coded OFDM and spread OFDM systems in correlated Rayleigh fading channels are presented. A channel statistic, namely the number of faded bits per OFDM symbol, is theoretically derived, and it is demonstrated that the distribution of this channel statistic can be used to determine how close the correlated channel performance is going to be to that of the uncorrelated fading channel.

Low Complexity MIMO-LDPC CDMA Systems over Multipath Channels

This paper proposes a low complexity composite CDMA system based on MIMO (Multiple-Input-Multiple-Output) processing and LDPC (low-density parity-check) codec based a CDMA system, which works well even if the complicated case of multipath, multiusers and short length LDPC codes. To explore the practical application, the mobile user in the composite CDMA systems is with only two antennas and adopts short length irregular LDPC codec, each user's data has been divided two LDPC encoded substreams being sent to two transmitter antennas at base station. Since the LDPC encoded substreams of reaching the mobile user are orthogonal to each other in space and time, the CDMA system performances (BER and SINR) can be improved much, but the multipath may ruin the orthogonalilty. To solve the problems, the paper provides the algorithms of main function modules of transmitter and receivers, gives a simple method to test the girth of LDPC codes, and analyzes the performance of MIMO-LDPC CDMA systems theoretically and experimentally. The simulation results show that the hybrid CDMA systems can have better performance than the conventional CDMA systems based on single transmitted antenna at a base station.